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Commit a86a3aa5 authored by Martin K. Petersen's avatar Martin K. Petersen
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Merge patch series "mpi3mr: Few Enhancements and minor fixes" 

Ranjan Kumar <ranjan.kumar@broadcom.com> says:

Few Enhancements and minor fixes of mpi3mr driver.

Link: https://lore.kernel.org/r/20240313100746.128951-1-ranjan.kumar@broadcom.comSigned-off-by: default avatarMartin K. Petersen <martin.petersen@oracle.com>
parents e831b92b 829dce7e
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Showing with 72 additions and 54 deletions
drivers/scsi/mpi3mr/mpi/mpi30_cnfg.h
View file @ a86a3aa5
...@@ -309,6 +309,7 @@ struct mpi3_man6_gpio_entry { ...@@ -309,6 +309,7 @@ struct mpi3_man6_gpio_entry {
#define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_SOURCE_GENERIC (0x00) #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_SOURCE_GENERIC (0x00)
#define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_SOURCE_CABLE_MGMT (0x10) #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_SOURCE_CABLE_MGMT (0x10)
#define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_SOURCE_ACTIVE_CABLE_OVERCURRENT (0x20) #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_SOURCE_ACTIVE_CABLE_OVERCURRENT (0x20)
#define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_ACK_REQUIRED (0x02)
#define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_TRIGGER_MASK (0x01) #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_TRIGGER_MASK (0x01)
#define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_TRIGGER_EDGE (0x00) #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_TRIGGER_EDGE (0x00)
#define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_TRIGGER_LEVEL (0x01) #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_TRIGGER_LEVEL (0x01)
...@@ -1315,6 +1316,8 @@ struct mpi3_driver_page0 { ...@@ -1315,6 +1316,8 @@ struct mpi3_driver_page0 {
__le32 reserved18; __le32 reserved18;
}; };
#define MPI3_DRIVER0_PAGEVERSION (0x00) #define MPI3_DRIVER0_PAGEVERSION (0x00)
#define MPI3_DRIVER0_BSDOPTS_DEVICEEXPOSURE_DISABLE (0x00000020)
#define MPI3_DRIVER0_BSDOPTS_WRITECACHE_DISABLE (0x00000010)
#define MPI3_DRIVER0_BSDOPTS_HEADLESS_MODE_ENABLE (0x00000008) #define MPI3_DRIVER0_BSDOPTS_HEADLESS_MODE_ENABLE (0x00000008)
#define MPI3_DRIVER0_BSDOPTS_DIS_HII_CONFIG_UTIL (0x00000004) #define MPI3_DRIVER0_BSDOPTS_DIS_HII_CONFIG_UTIL (0x00000004)
#define MPI3_DRIVER0_BSDOPTS_REGISTRATION_MASK (0x00000003) #define MPI3_DRIVER0_BSDOPTS_REGISTRATION_MASK (0x00000003)
......
drivers/scsi/mpi3mr/mpi/mpi30_image.h
View file @ a86a3aa5
...@@ -198,16 +198,17 @@ struct mpi3_supported_devices_data { ...@@ -198,16 +198,17 @@ struct mpi3_supported_devices_data {
struct mpi3_supported_device supported_device[MPI3_SUPPORTED_DEVICE_MAX]; struct mpi3_supported_device supported_device[MPI3_SUPPORTED_DEVICE_MAX];
}; };
#ifndef MPI3_ENCRYPTED_HASH_MAX #ifndef MPI3_PUBLIC_KEY_MAX
#define MPI3_ENCRYPTED_HASH_MAX (1) #define MPI3_PUBLIC_KEY_MAX (1)
#endif #endif
struct mpi3_encrypted_hash_entry { struct mpi3_encrypted_hash_entry {
u8 hash_image_type; u8 hash_image_type;
u8 hash_algorithm; u8 hash_algorithm;
u8 encryption_algorithm; u8 encryption_algorithm;
u8 reserved03; u8 reserved03;
__le32 reserved04; __le16 public_key_size;
__le32 encrypted_hash[MPI3_ENCRYPTED_HASH_MAX]; __le16 signature_size;
__le32 public_key[MPI3_PUBLIC_KEY_MAX];
}; };
#define MPI3_HASH_IMAGE_TYPE_KEY_WITH_SIGNATURE (0x03) #define MPI3_HASH_IMAGE_TYPE_KEY_WITH_SIGNATURE (0x03)
...@@ -228,17 +229,6 @@ struct mpi3_encrypted_hash_entry { ...@@ -228,17 +229,6 @@ struct mpi3_encrypted_hash_entry {
#define MPI3_ENCRYPTION_ALGORITHM_RSA2048 (0x04) #define MPI3_ENCRYPTION_ALGORITHM_RSA2048 (0x04)
#define MPI3_ENCRYPTION_ALGORITHM_RSA4096 (0x05) #define MPI3_ENCRYPTION_ALGORITHM_RSA4096 (0x05)
#define MPI3_ENCRYPTION_ALGORITHM_RSA3072 (0x06) #define MPI3_ENCRYPTION_ALGORITHM_RSA3072 (0x06)
#ifndef MPI3_PUBLIC_KEY_MAX
#define MPI3_PUBLIC_KEY_MAX (1)
#endif
struct mpi3_encrypted_key_with_hash_entry {
u8 hash_image_type;
u8 hash_algorithm;
u8 encryption_algorithm;
u8 reserved03;
__le32 reserved04;
__le32 public_key[MPI3_PUBLIC_KEY_MAX];
};
#ifndef MPI3_ENCRYPTED_HASH_ENTRY_MAX #ifndef MPI3_ENCRYPTED_HASH_ENTRY_MAX
#define MPI3_ENCRYPTED_HASH_ENTRY_MAX (1) #define MPI3_ENCRYPTED_HASH_ENTRY_MAX (1)
......
drivers/scsi/mpi3mr/mpi/mpi30_ioc.h
View file @ a86a3aa5
...@@ -27,7 +27,7 @@ struct mpi3_ioc_init_request { ...@@ -27,7 +27,7 @@ struct mpi3_ioc_init_request {
__le64 sense_buffer_free_queue_address; __le64 sense_buffer_free_queue_address;
__le64 driver_information_address; __le64 driver_information_address;
}; };
#define MPI3_IOCINIT_MSGFLAGS_WRITESAMEDIVERT_SUPPORTED (0x08)
#define MPI3_IOCINIT_MSGFLAGS_SCSIIOSTATUSREPLY_SUPPORTED (0x04) #define MPI3_IOCINIT_MSGFLAGS_SCSIIOSTATUSREPLY_SUPPORTED (0x04)
#define MPI3_IOCINIT_MSGFLAGS_HOSTMETADATA_MASK (0x03) #define MPI3_IOCINIT_MSGFLAGS_HOSTMETADATA_MASK (0x03)
#define MPI3_IOCINIT_MSGFLAGS_HOSTMETADATA_NOT_USED (0x00) #define MPI3_IOCINIT_MSGFLAGS_HOSTMETADATA_NOT_USED (0x00)
...@@ -101,6 +101,8 @@ struct mpi3_ioc_facts_data { ...@@ -101,6 +101,8 @@ struct mpi3_ioc_facts_data {
__le16 max_io_throttle_group; __le16 max_io_throttle_group;
__le16 io_throttle_low; __le16 io_throttle_low;
__le16 io_throttle_high; __le16 io_throttle_high;
__le32 diag_fdl_size;
__le32 diag_tty_size;
}; };
#define MPI3_IOCFACTS_CAPABILITY_NON_SUPERVISOR_MASK (0x80000000) #define MPI3_IOCFACTS_CAPABILITY_NON_SUPERVISOR_MASK (0x80000000)
#define MPI3_IOCFACTS_CAPABILITY_SUPERVISOR_IOC (0x00000000) #define MPI3_IOCFACTS_CAPABILITY_SUPERVISOR_IOC (0x00000000)
...@@ -108,13 +110,13 @@ struct mpi3_ioc_facts_data { ...@@ -108,13 +110,13 @@ struct mpi3_ioc_facts_data {
#define MPI3_IOCFACTS_CAPABILITY_INT_COALESCE_MASK (0x00000600) #define MPI3_IOCFACTS_CAPABILITY_INT_COALESCE_MASK (0x00000600)
#define MPI3_IOCFACTS_CAPABILITY_INT_COALESCE_FIXED_THRESHOLD (0x00000000) #define MPI3_IOCFACTS_CAPABILITY_INT_COALESCE_FIXED_THRESHOLD (0x00000000)
#define MPI3_IOCFACTS_CAPABILITY_INT_COALESCE_OUTSTANDING_IO (0x00000200) #define MPI3_IOCFACTS_CAPABILITY_INT_COALESCE_OUTSTANDING_IO (0x00000200)
#define MPI3_IOCFACTS_CAPABILITY_COMPLETE_RESET_CAPABLE (0x00000100) #define MPI3_IOCFACTS_CAPABILITY_COMPLETE_RESET_SUPPORTED (0x00000100)
#define MPI3_IOCFACTS_CAPABILITY_SEG_DIAG_TRACE_ENABLED (0x00000080) #define MPI3_IOCFACTS_CAPABILITY_SEG_DIAG_TRACE_SUPPORTED (0x00000080)
#define MPI3_IOCFACTS_CAPABILITY_SEG_DIAG_FW_ENABLED (0x00000040) #define MPI3_IOCFACTS_CAPABILITY_SEG_DIAG_FW_SUPPORTED (0x00000040)
#define MPI3_IOCFACTS_CAPABILITY_SEG_DIAG_DRIVER_ENABLED (0x00000020) #define MPI3_IOCFACTS_CAPABILITY_SEG_DIAG_DRIVER_SUPPORTED (0x00000020)
#define MPI3_IOCFACTS_CAPABILITY_ADVANCED_HOST_PD_ENABLED (0x00000010) #define MPI3_IOCFACTS_CAPABILITY_ADVANCED_HOST_PD_SUPPORTED (0x00000010)
#define MPI3_IOCFACTS_CAPABILITY_RAID_CAPABLE (0x00000008) #define MPI3_IOCFACTS_CAPABILITY_RAID_SUPPORTED (0x00000008)
#define MPI3_IOCFACTS_CAPABILITY_MULTIPATH_ENABLED (0x00000002) #define MPI3_IOCFACTS_CAPABILITY_MULTIPATH_SUPPORTED (0x00000002)
#define MPI3_IOCFACTS_CAPABILITY_COALESCE_CTRL_SUPPORTED (0x00000001) #define MPI3_IOCFACTS_CAPABILITY_COALESCE_CTRL_SUPPORTED (0x00000001)
#define MPI3_IOCFACTS_PID_TYPE_MASK (0xf000) #define MPI3_IOCFACTS_PID_TYPE_MASK (0xf000)
#define MPI3_IOCFACTS_PID_TYPE_SHIFT (12) #define MPI3_IOCFACTS_PID_TYPE_SHIFT (12)
...@@ -159,6 +161,8 @@ struct mpi3_ioc_facts_data { ...@@ -159,6 +161,8 @@ struct mpi3_ioc_facts_data {
#define MPI3_IOCFACTS_FLAGS_PERSONALITY_RAID_DDR (0x00000002) #define MPI3_IOCFACTS_FLAGS_PERSONALITY_RAID_DDR (0x00000002)
#define MPI3_IOCFACTS_IO_THROTTLE_DATA_LENGTH_NOT_REQUIRED (0x0000) #define MPI3_IOCFACTS_IO_THROTTLE_DATA_LENGTH_NOT_REQUIRED (0x0000)
#define MPI3_IOCFACTS_MAX_IO_THROTTLE_GROUP_NOT_REQUIRED (0x0000) #define MPI3_IOCFACTS_MAX_IO_THROTTLE_GROUP_NOT_REQUIRED (0x0000)
#define MPI3_IOCFACTS_DIAGFDLSIZE_NOT_SUPPORTED (0x00000000)
#define MPI3_IOCFACTS_DIAGTTYSIZE_NOT_SUPPORTED (0x00000000)
struct mpi3_mgmt_passthrough_request { struct mpi3_mgmt_passthrough_request {
__le16 host_tag; __le16 host_tag;
u8 ioc_use_only02; u8 ioc_use_only02;
......
drivers/scsi/mpi3mr/mpi/mpi30_transport.h
View file @ a86a3aa5
...@@ -18,7 +18,7 @@ union mpi3_version_union { ...@@ -18,7 +18,7 @@ union mpi3_version_union {
#define MPI3_VERSION_MAJOR (3) #define MPI3_VERSION_MAJOR (3)
#define MPI3_VERSION_MINOR (0) #define MPI3_VERSION_MINOR (0)
#define MPI3_VERSION_UNIT (28) #define MPI3_VERSION_UNIT (31)
#define MPI3_VERSION_DEV (0) #define MPI3_VERSION_DEV (0)
#define MPI3_DEVHANDLE_INVALID (0xffff) #define MPI3_DEVHANDLE_INVALID (0xffff)
struct mpi3_sysif_oper_queue_indexes { struct mpi3_sysif_oper_queue_indexes {
......
drivers/scsi/mpi3mr/mpi3mr.h
View file @ a86a3aa5
...@@ -55,15 +55,15 @@ extern struct list_head mrioc_list; ...@@ -55,15 +55,15 @@ extern struct list_head mrioc_list;
extern int prot_mask; extern int prot_mask;
extern atomic64_t event_counter; extern atomic64_t event_counter;
#define MPI3MR_DRIVER_VERSION "8.5.1.0.0" #define MPI3MR_DRIVER_VERSION "8.8.1.0.50"
#define MPI3MR_DRIVER_RELDATE "5-December-2023" #define MPI3MR_DRIVER_RELDATE "5-March-2024"
#define MPI3MR_DRIVER_NAME "mpi3mr" #define MPI3MR_DRIVER_NAME "mpi3mr"
#define MPI3MR_DRIVER_LICENSE "GPL" #define MPI3MR_DRIVER_LICENSE "GPL"
#define MPI3MR_DRIVER_AUTHOR "Broadcom Inc. <mpi3mr-linuxdrv.pdl@broadcom.com>" #define MPI3MR_DRIVER_AUTHOR "Broadcom Inc. <mpi3mr-linuxdrv.pdl@broadcom.com>"
#define MPI3MR_DRIVER_DESC "MPI3 Storage Controller Device Driver" #define MPI3MR_DRIVER_DESC "MPI3 Storage Controller Device Driver"
#define MPI3MR_NAME_LENGTH 32 #define MPI3MR_NAME_LENGTH 64
#define IOCNAME "%s: " #define IOCNAME "%s: "
#define MPI3MR_DEFAULT_MAX_IO_SIZE (1 * 1024 * 1024) #define MPI3MR_DEFAULT_MAX_IO_SIZE (1 * 1024 * 1024)
...@@ -294,6 +294,10 @@ enum mpi3mr_reset_reason { ...@@ -294,6 +294,10 @@ enum mpi3mr_reset_reason {
MPI3MR_RESET_FROM_SAS_TRANSPORT_TIMEOUT = 30, MPI3MR_RESET_FROM_SAS_TRANSPORT_TIMEOUT = 30,
}; };
#define MPI3MR_RESET_REASON_OSTYPE_LINUX 1
#define MPI3MR_RESET_REASON_OSTYPE_SHIFT 28
#define MPI3MR_RESET_REASON_IOCNUM_SHIFT 20
/* Queue type definitions */ /* Queue type definitions */
enum queue_type { enum queue_type {
MPI3MR_DEFAULT_QUEUE = 0, MPI3MR_DEFAULT_QUEUE = 0,
...@@ -1142,7 +1146,7 @@ struct mpi3mr_ioc { ...@@ -1142,7 +1146,7 @@ struct mpi3mr_ioc {
spinlock_t fwevt_lock; spinlock_t fwevt_lock;
struct list_head fwevt_list; struct list_head fwevt_list;
char watchdog_work_q_name[20]; char watchdog_work_q_name[50];
struct workqueue_struct *watchdog_work_q; struct workqueue_struct *watchdog_work_q;
struct delayed_work watchdog_work; struct delayed_work watchdog_work;
spinlock_t watchdog_lock; spinlock_t watchdog_lock;
...@@ -1336,7 +1340,7 @@ void mpi3mr_start_watchdog(struct mpi3mr_ioc *mrioc); ...@@ -1336,7 +1340,7 @@ void mpi3mr_start_watchdog(struct mpi3mr_ioc *mrioc);
void mpi3mr_stop_watchdog(struct mpi3mr_ioc *mrioc); void mpi3mr_stop_watchdog(struct mpi3mr_ioc *mrioc);
int mpi3mr_soft_reset_handler(struct mpi3mr_ioc *mrioc, int mpi3mr_soft_reset_handler(struct mpi3mr_ioc *mrioc,
u32 reset_reason, u8 snapdump); u16 reset_reason, u8 snapdump);
void mpi3mr_ioc_disable_intr(struct mpi3mr_ioc *mrioc); void mpi3mr_ioc_disable_intr(struct mpi3mr_ioc *mrioc);
void mpi3mr_ioc_enable_intr(struct mpi3mr_ioc *mrioc); void mpi3mr_ioc_enable_intr(struct mpi3mr_ioc *mrioc);
...@@ -1348,7 +1352,7 @@ void mpi3mr_wait_for_host_io(struct mpi3mr_ioc *mrioc, u32 timeout); ...@@ -1348,7 +1352,7 @@ void mpi3mr_wait_for_host_io(struct mpi3mr_ioc *mrioc, u32 timeout);
void mpi3mr_cleanup_fwevt_list(struct mpi3mr_ioc *mrioc); void mpi3mr_cleanup_fwevt_list(struct mpi3mr_ioc *mrioc);
void mpi3mr_flush_host_io(struct mpi3mr_ioc *mrioc); void mpi3mr_flush_host_io(struct mpi3mr_ioc *mrioc);
void mpi3mr_invalidate_devhandles(struct mpi3mr_ioc *mrioc); void mpi3mr_invalidate_devhandles(struct mpi3mr_ioc *mrioc);
void mpi3mr_rfresh_tgtdevs(struct mpi3mr_ioc *mrioc); void mpi3mr_refresh_tgtdevs(struct mpi3mr_ioc *mrioc);
void mpi3mr_flush_delayed_cmd_lists(struct mpi3mr_ioc *mrioc); void mpi3mr_flush_delayed_cmd_lists(struct mpi3mr_ioc *mrioc);
void mpi3mr_check_rh_fault_ioc(struct mpi3mr_ioc *mrioc, u32 reason_code); void mpi3mr_check_rh_fault_ioc(struct mpi3mr_ioc *mrioc, u32 reason_code);
void mpi3mr_print_fault_info(struct mpi3mr_ioc *mrioc); void mpi3mr_print_fault_info(struct mpi3mr_ioc *mrioc);
......
drivers/scsi/mpi3mr/mpi3mr_app.c
View file @ a86a3aa5
...@@ -1598,26 +1598,33 @@ static long mpi3mr_bsg_process_mpt_cmds(struct bsg_job *job) ...@@ -1598,26 +1598,33 @@ static long mpi3mr_bsg_process_mpt_cmds(struct bsg_job *job)
rval = -EAGAIN; rval = -EAGAIN;
if (mrioc->bsg_cmds.state & MPI3MR_CMD_RESET) if (mrioc->bsg_cmds.state & MPI3MR_CMD_RESET)
goto out_unlock; goto out_unlock;
dprint_bsg_err(mrioc, if (((mpi_header->function != MPI3_FUNCTION_SCSI_IO) &&
"%s: bsg request timedout after %d seconds\n", __func__, (mpi_header->function != MPI3_FUNCTION_NVME_ENCAPSULATED))
karg->timeout); || (mrioc->logging_level & MPI3_DEBUG_BSG_ERROR)) {
if (mrioc->logging_level & MPI3_DEBUG_BSG_ERROR) { ioc_info(mrioc, "%s: bsg request timedout after %d seconds\n",
dprint_dump(mpi_req, MPI3MR_ADMIN_REQ_FRAME_SZ, __func__, karg->timeout);
if (!(mrioc->logging_level & MPI3_DEBUG_BSG_INFO)) {
dprint_dump(mpi_req, MPI3MR_ADMIN_REQ_FRAME_SZ,
"bsg_mpi3_req"); "bsg_mpi3_req");
if (mpi_header->function == if (mpi_header->function ==
MPI3_BSG_FUNCTION_MGMT_PASSTHROUGH) { MPI3_FUNCTION_MGMT_PASSTHROUGH) {
drv_buf_iter = &drv_bufs[0]; drv_buf_iter = &drv_bufs[0];
dprint_dump(drv_buf_iter->kern_buf, dprint_dump(drv_buf_iter->kern_buf,
rmc_size, "mpi3_mgmt_req"); rmc_size, "mpi3_mgmt_req");
}
} }
} }
if ((mpi_header->function == MPI3_BSG_FUNCTION_NVME_ENCAPSULATED) || if ((mpi_header->function == MPI3_BSG_FUNCTION_NVME_ENCAPSULATED) ||
(mpi_header->function == MPI3_BSG_FUNCTION_SCSI_IO)) (mpi_header->function == MPI3_BSG_FUNCTION_SCSI_IO)) {
dprint_bsg_err(mrioc, "%s: bsg request timedout after %d seconds,\n"
"issuing target reset to (0x%04x)\n", __func__,
karg->timeout, mpi_header->function_dependent);
mpi3mr_issue_tm(mrioc, mpi3mr_issue_tm(mrioc,
MPI3_SCSITASKMGMT_TASKTYPE_TARGET_RESET, MPI3_SCSITASKMGMT_TASKTYPE_TARGET_RESET,
mpi_header->function_dependent, 0, mpi_header->function_dependent, 0,
MPI3MR_HOSTTAG_BLK_TMS, MPI3MR_RESETTM_TIMEOUT, MPI3MR_HOSTTAG_BLK_TMS, MPI3MR_RESETTM_TIMEOUT,
&mrioc->host_tm_cmds, &resp_code, NULL); &mrioc->host_tm_cmds, &resp_code, NULL);
}
if (!(mrioc->bsg_cmds.state & MPI3MR_CMD_COMPLETE) && if (!(mrioc->bsg_cmds.state & MPI3MR_CMD_COMPLETE) &&
!(mrioc->bsg_cmds.state & MPI3MR_CMD_RESET)) !(mrioc->bsg_cmds.state & MPI3MR_CMD_RESET))
mpi3mr_soft_reset_handler(mrioc, mpi3mr_soft_reset_handler(mrioc,
......
drivers/scsi/mpi3mr/mpi3mr_fw.c
View file @ a86a3aa5
...@@ -11,7 +11,7 @@ ...@@ -11,7 +11,7 @@
#include <linux/io-64-nonatomic-lo-hi.h> #include <linux/io-64-nonatomic-lo-hi.h>
static int static int
mpi3mr_issue_reset(struct mpi3mr_ioc *mrioc, u16 reset_type, u32 reset_reason); mpi3mr_issue_reset(struct mpi3mr_ioc *mrioc, u16 reset_type, u16 reset_reason);
static int mpi3mr_setup_admin_qpair(struct mpi3mr_ioc *mrioc); static int mpi3mr_setup_admin_qpair(struct mpi3mr_ioc *mrioc);
static void mpi3mr_process_factsdata(struct mpi3mr_ioc *mrioc, static void mpi3mr_process_factsdata(struct mpi3mr_ioc *mrioc,
struct mpi3_ioc_facts_data *facts_data); struct mpi3_ioc_facts_data *facts_data);
...@@ -1195,7 +1195,7 @@ static inline void mpi3mr_clear_reset_history(struct mpi3mr_ioc *mrioc) ...@@ -1195,7 +1195,7 @@ static inline void mpi3mr_clear_reset_history(struct mpi3mr_ioc *mrioc)
static int mpi3mr_issue_and_process_mur(struct mpi3mr_ioc *mrioc, static int mpi3mr_issue_and_process_mur(struct mpi3mr_ioc *mrioc,
u32 reset_reason) u32 reset_reason)
{ {
u32 ioc_config, timeout, ioc_status; u32 ioc_config, timeout, ioc_status, scratch_pad0;
int retval = -1; int retval = -1;
ioc_info(mrioc, "Issuing Message unit Reset(MUR)\n"); ioc_info(mrioc, "Issuing Message unit Reset(MUR)\n");
...@@ -1204,7 +1204,11 @@ static int mpi3mr_issue_and_process_mur(struct mpi3mr_ioc *mrioc, ...@@ -1204,7 +1204,11 @@ static int mpi3mr_issue_and_process_mur(struct mpi3mr_ioc *mrioc,
return retval; return retval;
} }
mpi3mr_clear_reset_history(mrioc); mpi3mr_clear_reset_history(mrioc);
writel(reset_reason, &mrioc->sysif_regs->scratchpad[0]); scratch_pad0 = ((MPI3MR_RESET_REASON_OSTYPE_LINUX <<
MPI3MR_RESET_REASON_OSTYPE_SHIFT) |
(mrioc->facts.ioc_num <<
MPI3MR_RESET_REASON_IOCNUM_SHIFT) | reset_reason);
writel(scratch_pad0, &mrioc->sysif_regs->scratchpad[0]);
ioc_config = readl(&mrioc->sysif_regs->ioc_configuration); ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
ioc_config &= ~MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC; ioc_config &= ~MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC;
writel(ioc_config, &mrioc->sysif_regs->ioc_configuration); writel(ioc_config, &mrioc->sysif_regs->ioc_configuration);
...@@ -1276,7 +1280,7 @@ mpi3mr_revalidate_factsdata(struct mpi3mr_ioc *mrioc) ...@@ -1276,7 +1280,7 @@ mpi3mr_revalidate_factsdata(struct mpi3mr_ioc *mrioc)
mrioc->shost->max_sectors * 512, mrioc->facts.max_data_length); mrioc->shost->max_sectors * 512, mrioc->facts.max_data_length);
if ((mrioc->sas_transport_enabled) && (mrioc->facts.ioc_capabilities & if ((mrioc->sas_transport_enabled) && (mrioc->facts.ioc_capabilities &
MPI3_IOCFACTS_CAPABILITY_MULTIPATH_ENABLED)) MPI3_IOCFACTS_CAPABILITY_MULTIPATH_SUPPORTED))
ioc_err(mrioc, ioc_err(mrioc,
"critical error: multipath capability is enabled at the\n" "critical error: multipath capability is enabled at the\n"
"\tcontroller while sas transport support is enabled at the\n" "\tcontroller while sas transport support is enabled at the\n"
...@@ -1520,11 +1524,11 @@ static inline void mpi3mr_set_diagsave(struct mpi3mr_ioc *mrioc) ...@@ -1520,11 +1524,11 @@ static inline void mpi3mr_set_diagsave(struct mpi3mr_ioc *mrioc)
* Return: 0 on success, non-zero on failure. * Return: 0 on success, non-zero on failure.
*/ */
static int mpi3mr_issue_reset(struct mpi3mr_ioc *mrioc, u16 reset_type, static int mpi3mr_issue_reset(struct mpi3mr_ioc *mrioc, u16 reset_type,
u32 reset_reason) u16 reset_reason)
{ {
int retval = -1; int retval = -1;
u8 unlock_retry_count = 0; u8 unlock_retry_count = 0;
u32 host_diagnostic, ioc_status, ioc_config; u32 host_diagnostic, ioc_status, ioc_config, scratch_pad0;
u32 timeout = MPI3MR_RESET_ACK_TIMEOUT * 10; u32 timeout = MPI3MR_RESET_ACK_TIMEOUT * 10;
if ((reset_type != MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET) && if ((reset_type != MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET) &&
...@@ -1576,6 +1580,9 @@ static int mpi3mr_issue_reset(struct mpi3mr_ioc *mrioc, u16 reset_type, ...@@ -1576,6 +1580,9 @@ static int mpi3mr_issue_reset(struct mpi3mr_ioc *mrioc, u16 reset_type,
unlock_retry_count, host_diagnostic); unlock_retry_count, host_diagnostic);
} while (!(host_diagnostic & MPI3_SYSIF_HOST_DIAG_DIAG_WRITE_ENABLE)); } while (!(host_diagnostic & MPI3_SYSIF_HOST_DIAG_DIAG_WRITE_ENABLE));
scratch_pad0 = ((MPI3MR_RESET_REASON_OSTYPE_LINUX <<
MPI3MR_RESET_REASON_OSTYPE_SHIFT) | (mrioc->facts.ioc_num <<
MPI3MR_RESET_REASON_IOCNUM_SHIFT) | reset_reason);
writel(reset_reason, &mrioc->sysif_regs->scratchpad[0]); writel(reset_reason, &mrioc->sysif_regs->scratchpad[0]);
writel(host_diagnostic | reset_type, writel(host_diagnostic | reset_type,
&mrioc->sysif_regs->host_diagnostic); &mrioc->sysif_regs->host_diagnostic);
...@@ -2581,7 +2588,7 @@ static void mpi3mr_watchdog_work(struct work_struct *work) ...@@ -2581,7 +2588,7 @@ static void mpi3mr_watchdog_work(struct work_struct *work)
unsigned long flags; unsigned long flags;
enum mpi3mr_iocstate ioc_state; enum mpi3mr_iocstate ioc_state;
u32 fault, host_diagnostic, ioc_status; u32 fault, host_diagnostic, ioc_status;
u32 reset_reason = MPI3MR_RESET_FROM_FAULT_WATCH; u16 reset_reason = MPI3MR_RESET_FROM_FAULT_WATCH;
if (mrioc->reset_in_progress) if (mrioc->reset_in_progress)
return; return;
...@@ -3302,6 +3309,8 @@ static int mpi3mr_issue_iocinit(struct mpi3mr_ioc *mrioc) ...@@ -3302,6 +3309,8 @@ static int mpi3mr_issue_iocinit(struct mpi3mr_ioc *mrioc)
iocinit_req.msg_flags |= iocinit_req.msg_flags |=
MPI3_IOCINIT_MSGFLAGS_SCSIIOSTATUSREPLY_SUPPORTED; MPI3_IOCINIT_MSGFLAGS_SCSIIOSTATUSREPLY_SUPPORTED;
iocinit_req.msg_flags |=
MPI3_IOCINIT_MSGFLAGS_WRITESAMEDIVERT_SUPPORTED;
init_completion(&mrioc->init_cmds.done); init_completion(&mrioc->init_cmds.done);
retval = mpi3mr_admin_request_post(mrioc, &iocinit_req, retval = mpi3mr_admin_request_post(mrioc, &iocinit_req,
...@@ -3668,8 +3677,8 @@ static const struct { ...@@ -3668,8 +3677,8 @@ static const struct {
u32 capability; u32 capability;
char *name; char *name;
} mpi3mr_capabilities[] = { } mpi3mr_capabilities[] = {
{ MPI3_IOCFACTS_CAPABILITY_RAID_CAPABLE, "RAID" }, { MPI3_IOCFACTS_CAPABILITY_RAID_SUPPORTED, "RAID" },
{ MPI3_IOCFACTS_CAPABILITY_MULTIPATH_ENABLED, "MultiPath" }, { MPI3_IOCFACTS_CAPABILITY_MULTIPATH_SUPPORTED, "MultiPath" },
}; };
/** /**
...@@ -3951,7 +3960,7 @@ int mpi3mr_init_ioc(struct mpi3mr_ioc *mrioc) ...@@ -3951,7 +3960,7 @@ int mpi3mr_init_ioc(struct mpi3mr_ioc *mrioc)
MPI3MR_HOST_IOS_KDUMP); MPI3MR_HOST_IOS_KDUMP);
if (!(mrioc->facts.ioc_capabilities & if (!(mrioc->facts.ioc_capabilities &
MPI3_IOCFACTS_CAPABILITY_MULTIPATH_ENABLED)) { MPI3_IOCFACTS_CAPABILITY_MULTIPATH_SUPPORTED)) {
mrioc->sas_transport_enabled = 1; mrioc->sas_transport_enabled = 1;
mrioc->scsi_device_channel = 1; mrioc->scsi_device_channel = 1;
mrioc->shost->max_channel = 1; mrioc->shost->max_channel = 1;
...@@ -4966,7 +4975,7 @@ void mpi3mr_pel_get_seqnum_complete(struct mpi3mr_ioc *mrioc, ...@@ -4966,7 +4975,7 @@ void mpi3mr_pel_get_seqnum_complete(struct mpi3mr_ioc *mrioc,
* Return: 0 on success, non-zero on failure. * Return: 0 on success, non-zero on failure.
*/ */
int mpi3mr_soft_reset_handler(struct mpi3mr_ioc *mrioc, int mpi3mr_soft_reset_handler(struct mpi3mr_ioc *mrioc,
u32 reset_reason, u8 snapdump) u16 reset_reason, u8 snapdump)
{ {
int retval = 0, i; int retval = 0, i;
unsigned long flags; unsigned long flags;
...@@ -5102,6 +5111,7 @@ int mpi3mr_soft_reset_handler(struct mpi3mr_ioc *mrioc, ...@@ -5102,6 +5111,7 @@ int mpi3mr_soft_reset_handler(struct mpi3mr_ioc *mrioc,
mrioc->device_refresh_on = 0; mrioc->device_refresh_on = 0;
mrioc->unrecoverable = 1; mrioc->unrecoverable = 1;
mrioc->reset_in_progress = 0; mrioc->reset_in_progress = 0;
mrioc->stop_bsgs = 0;
retval = -1; retval = -1;
mpi3mr_flush_cmds_for_unrecovered_controller(mrioc); mpi3mr_flush_cmds_for_unrecovered_controller(mrioc);
} }
......
drivers/scsi/mpi3mr/mpi3mr_os.c
View file @ a86a3aa5
...@@ -1029,7 +1029,7 @@ mpi3mr_update_sdev(struct scsi_device *sdev, void *data) ...@@ -1029,7 +1029,7 @@ mpi3mr_update_sdev(struct scsi_device *sdev, void *data)
} }
/** /**
* mpi3mr_rfresh_tgtdevs - Refresh target device exposure * mpi3mr_refresh_tgtdevs - Refresh target device exposure
* @mrioc: Adapter instance reference * @mrioc: Adapter instance reference
* *
* This is executed post controller reset to identify any * This is executed post controller reset to identify any
...@@ -1039,7 +1039,7 @@ mpi3mr_update_sdev(struct scsi_device *sdev, void *data) ...@@ -1039,7 +1039,7 @@ mpi3mr_update_sdev(struct scsi_device *sdev, void *data)
* Return: Nothing. * Return: Nothing.
*/ */
void mpi3mr_rfresh_tgtdevs(struct mpi3mr_ioc *mrioc) void mpi3mr_refresh_tgtdevs(struct mpi3mr_ioc *mrioc)
{ {
struct mpi3mr_tgt_dev *tgtdev, *tgtdev_next; struct mpi3mr_tgt_dev *tgtdev, *tgtdev_next;
struct mpi3mr_stgt_priv_data *tgt_priv; struct mpi3mr_stgt_priv_data *tgt_priv;
...@@ -1047,8 +1047,8 @@ void mpi3mr_rfresh_tgtdevs(struct mpi3mr_ioc *mrioc) ...@@ -1047,8 +1047,8 @@ void mpi3mr_rfresh_tgtdevs(struct mpi3mr_ioc *mrioc)
dprint_reset(mrioc, "refresh target devices: check for removals\n"); dprint_reset(mrioc, "refresh target devices: check for removals\n");
list_for_each_entry_safe(tgtdev, tgtdev_next, &mrioc->tgtdev_list, list_for_each_entry_safe(tgtdev, tgtdev_next, &mrioc->tgtdev_list,
list) { list) {
if ((tgtdev->dev_handle == MPI3MR_INVALID_DEV_HANDLE) && if (((tgtdev->dev_handle == MPI3MR_INVALID_DEV_HANDLE) ||
tgtdev->is_hidden && tgtdev->is_hidden) &&
tgtdev->host_exposed && tgtdev->starget && tgtdev->host_exposed && tgtdev->starget &&
tgtdev->starget->hostdata) { tgtdev->starget->hostdata) {
tgt_priv = tgtdev->starget->hostdata; tgt_priv = tgtdev->starget->hostdata;
...@@ -2010,7 +2010,7 @@ static void mpi3mr_fwevt_bh(struct mpi3mr_ioc *mrioc, ...@@ -2010,7 +2010,7 @@ static void mpi3mr_fwevt_bh(struct mpi3mr_ioc *mrioc,
mpi3mr_refresh_sas_ports(mrioc); mpi3mr_refresh_sas_ports(mrioc);
mpi3mr_refresh_expanders(mrioc); mpi3mr_refresh_expanders(mrioc);
} }
mpi3mr_rfresh_tgtdevs(mrioc); mpi3mr_refresh_tgtdevs(mrioc);
ioc_info(mrioc, ioc_info(mrioc,
"scan for non responding and newly added devices after soft reset completed\n"); "scan for non responding and newly added devices after soft reset completed\n");
break; break;
...@@ -4895,7 +4895,7 @@ static int mpi3mr_qcmd(struct Scsi_Host *shost, ...@@ -4895,7 +4895,7 @@ static int mpi3mr_qcmd(struct Scsi_Host *shost,
MPI3_SCSIIO_MSGFLAGS_DIVERT_TO_FIRMWARE; MPI3_SCSIIO_MSGFLAGS_DIVERT_TO_FIRMWARE;
scsiio_flags |= MPI3_SCSIIO_FLAGS_DIVERT_REASON_IO_THROTTLING; scsiio_flags |= MPI3_SCSIIO_FLAGS_DIVERT_REASON_IO_THROTTLING;
} }
scsiio_req->flags = cpu_to_le32(scsiio_flags); scsiio_req->flags |= cpu_to_le32(scsiio_flags);
if (mpi3mr_op_request_post(mrioc, op_req_q, if (mpi3mr_op_request_post(mrioc, op_req_q,
scmd_priv_data->mpi3mr_scsiio_req)) { scmd_priv_data->mpi3mr_scsiio_req)) {
......
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