Commit a8a921dd authored by Gregory CLEMENT's avatar Gregory CLEMENT Committed by Jason Cooper

ARM: mvebu: add Device Tree for the Armada 385 RD board

The Armada 385 RD board is the reference design board from Marvell
for the Armada 385 SoC. This commit adds a Device Tree description for
this board, which enables the following features:

 * Network interfaces
 * I2C bus
 * Serial port
 * SPI bus, with a SPI flash
 * PCIe interface
Signed-off-by: default avatarGregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: default avatarJason Cooper <jason@lakedaemon.net>
parent 0d2e6378
...@@ -152,7 +152,8 @@ dtb-$(CONFIG_MACH_ARMADA_370) += \ ...@@ -152,7 +152,8 @@ dtb-$(CONFIG_MACH_ARMADA_370) += \
dtb-$(CONFIG_MACH_ARMADA_375) += \ dtb-$(CONFIG_MACH_ARMADA_375) += \
armada-375-db.dtb armada-375-db.dtb
dtb-$(CONFIG_MACH_ARMADA_38X) += \ dtb-$(CONFIG_MACH_ARMADA_38X) += \
armada-385-db.dtb armada-385-db.dtb \
armada-385-rd.dtb
dtb-$(CONFIG_MACH_ARMADA_XP) += \ dtb-$(CONFIG_MACH_ARMADA_XP) += \
armada-xp-axpwifiap.dtb \ armada-xp-axpwifiap.dtb \
armada-xp-db.dtb \ armada-xp-db.dtb \
......
/*
* Device Tree file for Marvell Armada 385 Reference Design board
* (RD-88F6820-AP)
*
* Copyright (C) 2014 Marvell
*
* Gregory CLEMENT <gregory.clement@free-electrons.com>
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
/dts-v1/;
#include "armada-385.dtsi"
/ {
model = "Marvell Armada 385 Reference Design";
compatible = "marvell,a385-rd", "marvell,armada385", "marvell,armada38x";
chosen {
bootargs = "console=ttyS0,115200 earlyprintk";
};
memory {
device_type = "memory";
reg = <0x00000000 0x10000000>; /* 256 MB */
};
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
internal-regs {
spi@10600 {
status = "okay";
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p128";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <108000000>;
};
};
i2c@11000 {
status = "okay";
clock-frequency = <100000>;
};
serial@12000 {
clock-frequency = <200000000>;
status = "okay";
};
ethernet@30000 {
status = "okay";
phy = <&phy0>;
phy-mode = "rgmii-id";
};
ethernet@70000 {
status = "okay";
phy = <&phy1>;
phy-mode = "rgmii-id";
};
mdio {
phy0: ethernet-phy@0 {
reg = <0>;
};
phy1: ethernet-phy@1 {
reg = <1>;
};
};
};
pcie-controller {
status = "okay";
/*
* One PCIe units is accessible through
* standard PCIe slot on the board.
*/
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
};
};
};
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