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Commit a8f3740f authored by Linus Torvalds's avatar Linus Torvalds
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Merge tag 'dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc 

Pull ARM SoC device tree conversions from Arnd Bergmann:
 "These are device tree conversions for a number of platforms, with the
  intention of turning code from board files into device tree
  descriptions.  Notable changes are:

   - davinci bindings for pinctrl, MTD, RTC, watchdog and i2c

   - nomadik bindings for all devices, removing the board files

   - bcm2835 bindings for mmc and i2c

   - tegra bindings for hdmi, keyboard, audio, as well as some updates

   - at91 bindings for hardware ecc and for devices on RM9200

   - mxs bindings for cfa100xx

   - sunxi support for Miniand Hackberry board"

* tag 'dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (72 commits)
  Revert "sunxi: a10-cubieboard: Add user LEDs to the device tree"
  Revert "sunxi: a13-olinuxino: Add user LED to the device tree"
  clk: tegra: initialise parent of uart clocks
  ARM: tegra: remove clock-frequency properties from serial nodes
  clk: tegra: fix driver to match DT binding
  clk: tegra: local arrays should be static
  clk: tegra: Add missing spinlock for hclk and pclk
  clk: tegra: Implement locking for super clock
  clk: tegra: fix wrong clock index between se to sata_cold
  sunxi: a13-olinuxino: Add user LED to the device tree
  ARM: davinci: da850 DT: add support for machine reboot
  ARM: davinci: da850: add wdt DT node
  ARM: davinci: da850: add DT node for I2C0
  ARM: at91: at91sam9n12: add DT parameters to enable PMECC
  ARM: at91: at91sam9x5: add DT parameters to enable PMECC
  ARM: at91: add EMAC bindings to RM9200 DT
  ARM: at91: add SSC bindings to RM9200 DT
  ARM: at91: add MMC bindings to RM9200 DT
  ARM: at91: Animeo IP: enable watchdog support
  ARM: nomadik: fix OF compilation regression
  ...
parents 6c5096e5 89dfe564
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Documentation/devicetree/bindings/arm/ste-nomadik.txt 0 → 100644
View file @ a8f3740f
ST-Ericsson Nomadik Device Tree Bindings
For various board the "board" node may contain specific properties
that pertain to this particular board, such as board-specific GPIOs.
Boards with the Nomadik SoC include:
S8815 "MiniKit" manufactured by Calao Systems:
Required root node property:
compatible="calaosystems,usb-s8815";
Required node: usb-s8815
Example:
usb-s8815 {
ethernet-gpio {
gpios = <&gpio3 19 0x1>;
interrupts = <19 0x1>;
interrupt-parent = <&gpio3>;
};
mmcsd-gpio {
gpios = <&gpio3 16 0x1>;
};
};
Documentation/devicetree/bindings/arm/tegra.txt
View file @ a8f3740f
NVIDIA Tegra device tree bindings
-------------------------------------------
Boards with the tegra20 SoC shall have the following properties:
SoCs
-------------------------------------------
Required root node property:
Each device tree must specify which Tegra SoC it uses, using one of the
following compatible values:
compatible = "nvidia,tegra20";
nvidia,tegra20
nvidia,tegra30
Boards with the tegra30 SoC shall have the following properties:
Boards
-------------------------------------------
Required root node property:
Each device tree must specify which one or more of the following
board-specific compatible values:
compatible = "nvidia,tegra30";
ad,medcom-wide
ad,plutux
ad,tamonten
ad,tec
compal,paz00
compulab,trimslice
nvidia,beaver
nvidia,cardhu
nvidia,cardhu-a02
nvidia,cardhu-a04
nvidia,harmony
nvidia,seaboard
nvidia,ventana
nvidia,whistler
toradex,colibri_t20-512
toradex,iris
Documentation/devicetree/bindings/mtd/fsmc-nand.txt
View file @ a8f3740f
* FSMC NAND
Required properties:
- compatible : "st,spear600-fsmc-nand"
- compatible : "st,spear600-fsmc-nand", "stericsson,fsmc-nand"
- reg : Address range of the mtd chip
- reg-names: Should contain the reg names "fsmc_regs", "nand_data", "nand_addr" and "nand_cmd"
......
arch/arm/Kconfig
View file @ a8f3740f
......@@ -896,10 +896,12 @@ config ARCH_NOMADIK
select ARCH_REQUIRE_GPIOLIB
select ARM_AMBA
select ARM_VIC
select CLKSRC_NOMADIK_MTU
select COMMON_CLK
select CPU_ARM926T
select GENERIC_CLOCKEVENTS
select MIGHT_HAVE_CACHE_L2X0
select USE_OF
select PINCTRL
select PINCTRL_STN8815
select SPARSE_IRQ
......
arch/arm/boot/dts/Makefile
View file @ a8f3740f
......@@ -96,11 +96,13 @@ dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \
imx28-apf28dev.dtb \
imx28-apx4devkit.dtb \
imx28-cfa10036.dtb \
imx28-cfa10037.dtb \
imx28-cfa10049.dtb \
imx28-evk.dtb \
imx28-m28evk.dtb \
imx28-sps1.dtb \
imx28-tx28.dtb
dtb-$(CONFIG_ARCH_NOMADIK) += ste-nomadik-s8815.dtb
dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \
omap3-beagle.dtb \
omap3-beagle-xm.dtb \
......@@ -135,8 +137,10 @@ dtb-$(CONFIG_ARCH_SPEAR3XX)+= spear300-evb.dtb \
spear320-hmi.dtb
dtb-$(CONFIG_ARCH_SPEAR6XX)+= spear600-evb.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun4i-a10-cubieboard.dtb \
sun4i-a10-hackberry.dtb \
sun5i-a13-olinuxino.dtb
dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
tegra20-iris-512.dtb \
tegra20-medcom-wide.dtb \
tegra20-paz00.dtb \
tegra20-plutux.dtb \
......@@ -145,6 +149,7 @@ dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
tegra20-trimslice.dtb \
tegra20-ventana.dtb \
tegra20-whistler.dtb \
tegra30-beaver.dtb \
tegra30-cardhu-a02.dtb \
tegra30-cardhu-a04.dtb \
tegra114-dalmore.dtb \
......
arch/arm/boot/dts/animeo_ip.dts
View file @ a8f3740f
......@@ -78,6 +78,10 @@ slot@1 {
bus-width = <4>;
};
};
watchdog@fffffd40 {
status = "okay";
};
};
nand0: nand@40000000 {
......
arch/arm/boot/dts/at91rm9200.dtsi
View file @ a8f3740f
......@@ -29,6 +29,9 @@ aliases {
gpio3 = &pioD;
tcb0 = &tcb0;
tcb1 = &tcb1;
ssc0 = &ssc0;
ssc1 = &ssc1;
ssc2 = &ssc2;
};
cpus {
cpu@0 {
......@@ -88,6 +91,52 @@ tcb1: timer@fffa4000 {
interrupts = <20 4 0 21 4 0 22 4 0>;
};
mmc0: mmc@fffb4000 {
compatible = "atmel,hsmci";
reg = <0xfffb4000 0x4000>;
interrupts = <10 4 0>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
ssc0: ssc@fffd0000 {
compatible = "atmel,at91rm9200-ssc";
reg = <0xfffd0000 0x4000>;
interrupts = <14 4 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
status = "disable";
};
ssc1: ssc@fffd4000 {
compatible = "atmel,at91rm9200-ssc";
reg = <0xfffd4000 0x4000>;
interrupts = <15 4 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
status = "disable";
};
ssc2: ssc@fffd8000 {
compatible = "atmel,at91rm9200-ssc";
reg = <0xfffd8000 0x4000>;
interrupts = <16 4 5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ssc2_tx &pinctrl_ssc2_rx>;
status = "disable";
};
macb0: ethernet@fffbc000 {
compatible = "cdns,at91rm9200-emac", "cdns,emac";
reg = <0xfffbc000 0x4000>;
interrupts = <24 4 3>;
phy-mode = "rmii";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_macb_rmii>;
status = "disabled";
};
pinctrl@fffff400 {
#address-cells = <1>;
#size-cells = <1>;
......@@ -207,6 +256,115 @@ pinctrl_nand: nand-0 {
};
};
macb {
pinctrl_macb_rmii: macb_rmii-0 {
atmel,pins =
<0 7 0x1 0x0 /* PA7 periph A */
0 8 0x1 0x0 /* PA8 periph A */
0 9 0x1 0x0 /* PA9 periph A */
0 10 0x1 0x0 /* PA10 periph A */
0 11 0x1 0x0 /* PA11 periph A */
0 12 0x1 0x0 /* PA12 periph A */
0 13 0x1 0x0 /* PA13 periph A */
0 14 0x1 0x0 /* PA14 periph A */
0 15 0x1 0x0 /* PA15 periph A */
0 16 0x1 0x0>; /* PA16 periph A */
};
pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
atmel,pins =
<1 12 0x2 0x0 /* PB12 periph B */
1 13 0x2 0x0 /* PB13 periph B */
1 14 0x2 0x0 /* PB14 periph B */
1 15 0x2 0x0 /* PB15 periph B */
1 16 0x2 0x0 /* PB16 periph B */
1 17 0x2 0x0 /* PB17 periph B */
1 18 0x2 0x0 /* PB18 periph B */
1 19 0x2 0x0>; /* PB19 periph B */
};
};
mmc0 {
pinctrl_mmc0_clk: mmc0_clk-0 {
atmel,pins =
<0 27 0x1 0x0>; /* PA27 periph A */
};
pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 {
atmel,pins =
<0 28 0x1 0x1 /* PA28 periph A with pullup */
0 29 0x1 0x1>; /* PA29 periph A with pullup */
};
pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
atmel,pins =
<1 3 0x2 0x1 /* PB3 periph B with pullup */
1 4 0x2 0x1 /* PB4 periph B with pullup */
1 5 0x2 0x1>; /* PB5 periph B with pullup */
};
pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 {
atmel,pins =
<0 8 0x2 0x1 /* PA8 periph B with pullup */
0 9 0x2 0x1>; /* PA9 periph B with pullup */
};
pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 {
atmel,pins =
<0 10 0x2 0x1 /* PA10 periph B with pullup */
0 11 0x2 0x1 /* PA11 periph B with pullup */
0 12 0x2 0x1>; /* PA12 periph B with pullup */
};
};
ssc0 {
pinctrl_ssc0_tx: ssc0_tx-0 {
atmel,pins =
<1 0 0x1 0x0 /* PB0 periph A */
1 1 0x1 0x0 /* PB1 periph A */
1 2 0x1 0x0>; /* PB2 periph A */
};
pinctrl_ssc0_rx: ssc0_rx-0 {
atmel,pins =
<1 3 0x1 0x0 /* PB3 periph A */
1 4 0x1 0x0 /* PB4 periph A */
1 5 0x1 0x0>; /* PB5 periph A */
};
};
ssc1 {
pinctrl_ssc1_tx: ssc1_tx-0 {
atmel,pins =
<1 6 0x1 0x0 /* PB6 periph A */
1 7 0x1 0x0 /* PB7 periph A */
1 8 0x1 0x0>; /* PB8 periph A */
};
pinctrl_ssc1_rx: ssc1_rx-0 {
atmel,pins =
<1 9 0x1 0x0 /* PB9 periph A */
1 10 0x1 0x0 /* PB10 periph A */
1 11 0x1 0x0>; /* PB11 periph A */
};
};
ssc2 {
pinctrl_ssc2_tx: ssc2_tx-0 {
atmel,pins =
<1 12 0x1 0x0 /* PB12 periph A */
1 13 0x1 0x0 /* PB13 periph A */
1 14 0x1 0x0>; /* PB14 periph A */
};
pinctrl_ssc2_rx: ssc2_rx-0 {
atmel,pins =
<1 15 0x1 0x0 /* PB15 periph A */
1 16 0x1 0x0 /* PB16 periph A */
1 17 0x1 0x0>; /* PB17 periph A */
};
};
pioA: gpio@fffff400 {
compatible = "atmel,at91rm9200-gpio";
reg = <0xfffff400 0x200>;
......
arch/arm/boot/dts/at91rm9200ek.dts
View file @ a8f3740f
......@@ -44,6 +44,11 @@ &pinctrl_uart1_dcd
status = "okay";
};
macb0: ethernet@fffbc000 {
phy-mode = "rmii";
status = "okay";
};
usb1: gadget@fffb0000 {
atmel,vbus-gpio = <&pioD 4 0>;
status = "okay";
......
arch/arm/boot/dts/at91sam9n12.dtsi
View file @ a8f3740f
......@@ -382,8 +382,9 @@ nand0: nand@40000000 {
reg = < 0x40000000 0x10000000
0xffffe000 0x00000600
0xffffe600 0x00000200
0x00100000 0x00100000
0x00108000 0x00018000
>;
atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
atmel,nand-addr-offset = <21>;
atmel,nand-cmd-offset = <22>;
pinctrl-names = "default";
......
arch/arm/boot/dts/at91sam9n12ek.dts
View file @ a8f3740f
......@@ -71,7 +71,10 @@ pinctrl_board_mmc0: mmc0-board {
nand0: nand@40000000 {
nand-bus-width = <8>;
nand-ecc-mode = "soft";
nand-ecc-mode = "hw";
atmel,has-pmecc;
atmel,pmecc-cap = <2>;
atmel,pmecc-sector-size = <512>;
nand-on-flash-bbt;
status = "okay";
};
......
arch/arm/boot/dts/at91sam9x5.dtsi
View file @ a8f3740f
......@@ -512,7 +512,11 @@ nand0: nand@40000000 {
#address-cells = <1>;
#size-cells = <1>;
reg = <0x40000000 0x10000000
0xffffe000 0x600 /* PMECC Registers */
0xffffe600 0x200 /* PMECC Error Location Registers */
0x00108000 0x18000 /* PMECC looup table in ROM code */
>;
atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
atmel,nand-addr-offset = <21>;
atmel,nand-cmd-offset = <22>;
pinctrl-names = "default";
......
arch/arm/boot/dts/at91sam9x5cm.dtsi
View file @ a8f3740f
......@@ -26,7 +26,10 @@ main_clock: clock@0 {
ahb {
nand0: nand@40000000 {
nand-bus-width = <8>;
nand-ecc-mode = "soft";
nand-ecc-mode = "hw";
atmel,has-pmecc; /* Enable PMECC */
atmel,pmecc-cap = <2>;
atmel,pmecc-sector-size = <512>;
nand-on-flash-bbt;
status = "okay";
......
arch/arm/boot/dts/bcm2835-rpi-b.dts
View file @ a8f3740f
/dts-v1/;
/memreserve/ 0x0c000000 0x04000000;
/include/ "bcm2835.dtsi"
/ {
......@@ -25,3 +24,18 @@ alt3: alt3 {
brcm,function = <7>; /* alt3 */
};
};
&i2c0 {
status = "okay";
clock-frequency = <100000>;
};
&i2c1 {
status = "okay";
clock-frequency = <100000>;
};
&sdhci {
status = "okay";
bus-width = <4>;
};
arch/arm/boot/dts/bcm2835.dtsi
View file @ a8f3740f
......@@ -63,5 +63,49 @@ gpio: gpio {
interrupt-controller;
#interrupt-cells = <2>;
};
i2c0: i2c@20205000 {
compatible = "brcm,bcm2835-i2c";
reg = <0x7e205000 0x1000>;
interrupts = <2 21>;
clocks = <&clk_i2c>;
status = "disabled";
};
i2c1: i2c@20804000 {
compatible = "brcm,bcm2835-i2c";
reg = <0x7e804000 0x1000>;
interrupts = <2 21>;
clocks = <&clk_i2c>;
status = "disabled";
};
sdhci: sdhci {
compatible = "brcm,bcm2835-sdhci";
reg = <0x7e300000 0x100>;
interrupts = <2 30>;
clocks = <&clk_mmc>;
status = "disabled";
};
};
clocks {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
clk_mmc: mmc {
compatible = "fixed-clock";
reg = <0>;
#clock-cells = <0>;
clock-frequency = <100000000>;
};
clk_i2c: i2c {
compatible = "fixed-clock";
reg = <1>;
#clock-cells = <0>;
clock-frequency = <150000000>;
};
};
};
arch/arm/boot/dts/da850-evm.dts
View file @ a8f3740f
......@@ -15,6 +15,9 @@ / {
model = "DA850/AM1808/OMAP-L138 EVM";
soc {
pmx_core: pinmux@1c14120 {
status = "okay";
};
serial0: serial@1c42000 {
status = "okay";
};
......@@ -24,5 +27,22 @@ serial1: serial@1d0c000 {
serial2: serial@1d0d000 {
status = "okay";
};
rtc0: rtc@1c23000 {
status = "okay";
};
i2c0: i2c@1c22000 {
status = "okay";
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
};
wdt: wdt@1c21000 {
status = "okay";
};
};
nand_cs3@62000000 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&nand_cs3_pins>;
};
};
arch/arm/boot/dts/da850.dtsi
View file @ a8f3740f
......@@ -28,14 +28,47 @@ soc {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x01c00000 0x400000>;
interrupt-parent = <&intc>;
pmx_core: pinmux@1c14120 {
compatible = "pinctrl-single";
reg = <0x14120 0x50>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-single,bit-per-mux;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xffffffff>;
status = "disabled";
nand_cs3_pins: pinmux_nand_pins {
pinctrl-single,bits = <
/* EMA_OE, EMA_WE */
0x1c 0x00110000 0x00ff0000
/* EMA_CS[4],EMA_CS[3]*/
0x1c 0x00000110 0x00000ff0
/*
* EMA_D[0], EMA_D[1], EMA_D[2],
* EMA_D[3], EMA_D[4], EMA_D[5],
* EMA_D[6], EMA_D[7]
*/
0x24 0x11111111 0xffffffff
/* EMA_A[1], EMA_A[2] */
0x30 0x01100000 0x0ff00000
>;
};
i2c0_pins: pinmux_i2c0_pins {
pinctrl-single,bits = <
/* I2C0_SDA,I2C0_SCL */
0x10 0x00002200 0x0000ff00
>;
};
};
serial0: serial@1c42000 {
compatible = "ns16550a";
reg = <0x42000 0x100>;
clock-frequency = <150000000>;
reg-shift = <2>;
interrupts = <25>;
interrupt-parent = <&intc>;
status = "disabled";
};
serial1: serial@1d0c000 {
......@@ -44,7 +77,6 @@ serial1: serial@1d0c000 {
clock-frequency = <150000000>;
reg-shift = <2>;
interrupts = <53>;
interrupt-parent = <&intc>;
status = "disabled";
};
serial2: serial@1d0d000 {
......@@ -53,8 +85,40 @@ serial2: serial@1d0d000 {
clock-frequency = <150000000>;
reg-shift = <2>;
interrupts = <61>;
interrupt-parent = <&intc>;
status = "disabled";
};
rtc0: rtc@1c23000 {
compatible = "ti,da830-rtc";
reg = <0x23000 0x1000>;
interrupts = <19
19>;
status = "disabled";
};
i2c0: i2c@1c22000 {
compatible = "ti,davinci-i2c";
reg = <0x22000 0x1000>;
interrupts = <15>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
wdt: wdt@1c21000 {
compatible = "ti,davinci-wdt";
reg = <0x21000 0x1000>;
status = "disabled";
};
};
nand_cs3@62000000 {
compatible = "ti,davinci-nand";
reg = <0x62000000 0x807ff
0x68000000 0x8000>;
ti,davinci-chipselect = <1>;
ti,davinci-mask-ale = <0>;
ti,davinci-mask-cle = <0>;
ti,davinci-mask-chipsel = <0>;
ti,davinci-ecc-mode = "hw";
ti,davinci-ecc-bits = <4>;
ti,davinci-nand-use-bbt;
status = "disabled";
};
};
arch/arm/boot/dts/imx28-cfa10037.dts 0 → 100644
View file @ a8f3740f
/*
* Copyright 2012 Free Electrons
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/*
* The CFA-10049 is an expansion board for the CFA-10036 module, thus we
* need to include the CFA-10036 DTS.
*/
/include/ "imx28-cfa10036.dts"
/ {
model = "Crystalfontz CFA-10037 Board";
compatible = "crystalfontz,cfa10037", "crystalfontz,cfa10036", "fsl,imx28";
apb@80000000 {
apbh@80000000 {
pinctrl@80018000 {
pinctrl-names = "default", "default";
pinctrl-1 = <&hog_pins_cfa10037>;
hog_pins_cfa10037: hog-10037@0 {
reg = <0>;
fsl,pinmux-ids = <
0x0073 /* MX28_PAD_GPMI_D7__GPIO_0_7 */
0x2153 /* MX28_PAD_SSP2_D5__GPIO_2_21 */
>;
fsl,drive-strength = <0>;
fsl,voltage = <1>;
fsl,pull-up = <0>;
};
};
};
apbx@80040000 {
usbphy1: usbphy@8007e000 {
status = "okay";
};
};
};
ahb@80080000 {
usb1: usb@80090000 {
vbus-supply = <&reg_usb1_vbus>;
pinctrl-0 = <&usbphy1_pins_a>;
pinctrl-names = "default";
status = "okay";
};
mac0: ethernet@800f0000 {
phy-mode = "rmii";
pinctrl-names = "default";
pinctrl-0 = <&mac0_pins_a>;
phy-reset-gpios = <&gpio2 21 0>;
phy-reset-duration = <100>;
status = "okay";
};
};
regulators {
compatible = "simple-bus";
reg_usb1_vbus: usb1_vbus {
compatible = "regulator-fixed";
regulator-name = "usb1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio0 7 1>;
};
};
};
arch/arm/boot/dts/imx28-cfa10049.dts
View file @ a8f3740f
......@@ -23,69 +23,120 @@ apb@80000000 {
apbh@80000000 {
pinctrl@80018000 {
pinctrl-names = "default", "default";
pinctrl-1 = <&hog_pins_cfa10049>;
pinctrl-1 = <&hog_pins_cfa10049
&hog_pins_cfa10049_pullup>;
hog_pins_cfa10049: hog-10049@0 {
reg = <0>;
fsl,pinmux-ids = <
0x0073 /* MX28_PAD_GPMI_D7__GPIO_0_7 */
0x1153 /* MX28_PAD_LCD_D22__GPIO_1_21 */
0x1163 /* MX28_PAD_LCD_D22__GPIO_1_22 */
0x1173 /* MX28_PAD_LCD_D22__GPIO_1_23 */
0x2153 /* MX28_PAD_SSP2_D5__GPIO_2_21 */
0x3173 /* MX28_PAD_LCD_RESET__GPIO_3_23 */
>;
fsl,drive-strength = <0>;
fsl,voltage = <1>;
fsl,pull-up = <0>;
};
spi3_pins_cfa10049: spi3-cfa10049@0 {
hog_pins_cfa10049_pullup: hog-10049-pullup@0 {
reg = <0>;
fsl,pinmux-ids = <
0x0181 /* MX28_PAD_GPMI_RDN__SSP3_SCK */
0x01c1 /* MX28_PAD_GPMI_RESETN__SSP3_CMD */
0x0111 /* MX28_PAD_GPMI_CE1N__SSP3_D3 */
0x01a2 /* MX28_PAD_GPMI_ALE__SSP3_D4 */
0x01b2 /* MX28_PAD_GPMI_CLE__SSP3_D5 */
0x2133 /* MX28_PAD_SSP2_D3__GPIO_2_19 */
0x3183 /* MX28_PAD_I2C0_SCL__GPIO_3_24 */
0x3193 /* MX28_PAD_I2C0_SDA__GPIO_3_25 */
0x31a3 /* MX28_PAD_SAIF_SDATA0__GPIO_3_26 */
0x31e3 /* MX28_PAD_LCD_RESET__GPIO_3_30 */
>;
fsl,drive-strength = <1>;
fsl,drive-strength = <0>;
fsl,voltage = <1>;
fsl,pull-up = <1>;
};
};
ssp3: ssp@80016000 {
compatible = "fsl,imx28-spi";
pinctrl-names = "default";
pinctrl-0 = <&spi3_pins_cfa10049>;
status = "okay";
spi2_pins_cfa10049: spi2-cfa10049@0 {
reg = <0>;
fsl,pinmux-ids = <
0x2103 /* MX28_PAD_SSP2_SCK__GPIO_2_16 */
0x2113 /* MX28_PAD_SSP2_CMD__GPIO_2_17 */
0x2123 /* MX28_PAD_SSP2_D0__GPIO_2_18 */
>;
fsl,drive-strength = <1>;
fsl,voltage = <1>;
fsl,pull-up = <1>;
};
gpio5: gpio5@0 {
compatible = "fairchild,74hc595";
gpio-controller;
#gpio-cells = <2>;
spi3_pins_cfa10049: spi3-cfa10049@0 {
reg = <0>;
registers-number = <2>;
spi-max-frequency = <100000>;
fsl,pinmux-ids = <
0x0183 /* MX28_PAD_GPMI_RDN__GPIO_0_24 */
0x01c3 /* MX28_PAD_GPMI_RESETN__GPIO_0_28 */
0x0113 /* MX28_PAD_GPMI_CE1N__GPIO_0_17 */
0x01a3 /* MX28_PAD_GPMI_ALE__GPIO_0_26 */
0x01b3 /* MX28_PAD_GPMI_CLE__GPIO_0_27 */
>;
fsl,drive-strength = <1>;
fsl,voltage = <1>;
fsl,pull-up = <1>;
};
gpio6: gpio6@1 {
compatible = "fairchild,74hc595";
gpio-controller;
#gpio-cells = <2>;
reg = <1>;
registers-number = <4>;
spi-max-frequency = <100000>;
lcdif_18bit_pins_cfa10049: lcdif-18bit@0 {
reg = <0>;
fsl,pinmux-ids = <
0x1000 /* MX28_PAD_LCD_D00__LCD_D0 */
0x1010 /* MX28_PAD_LCD_D01__LCD_D1 */
0x1020 /* MX28_PAD_LCD_D02__LCD_D2 */
0x1030 /* MX28_PAD_LCD_D03__LCD_D3 */
0x1040 /* MX28_PAD_LCD_D04__LCD_D4 */
0x1050 /* MX28_PAD_LCD_D05__LCD_D5 */
0x1060 /* MX28_PAD_LCD_D06__LCD_D6 */
0x1070 /* MX28_PAD_LCD_D07__LCD_D7 */
0x1080 /* MX28_PAD_LCD_D08__LCD_D8 */
0x1090 /* MX28_PAD_LCD_D09__LCD_D9 */
0x10a0 /* MX28_PAD_LCD_D10__LCD_D10 */
0x10b0 /* MX28_PAD_LCD_D11__LCD_D11 */
0x10c0 /* MX28_PAD_LCD_D12__LCD_D12 */
0x10d0 /* MX28_PAD_LCD_D13__LCD_D13 */
0x10e0 /* MX28_PAD_LCD_D14__LCD_D14 */
0x10f0 /* MX28_PAD_LCD_D15__LCD_D15 */
0x1100 /* MX28_PAD_LCD_D16__LCD_D16 */
0x1110 /* MX28_PAD_LCD_D17__LCD_D17 */
>;
fsl,drive-strength = <0>;
fsl,voltage = <1>;
fsl,pull-up = <0>;
};
dac0: dh2228@2 {
compatible = "rohm,dh2228fv";
reg = <2>;
spi-max-frequency = <100000>;
lcdif_pins_cfa10049: lcdif-evk@0 {
reg = <0>;
fsl,pinmux-ids = <
0x1181 /* MX28_PAD_LCD_RD_E__LCD_VSYNC */
0x1191 /* MX28_PAD_LCD_WR_RWN__LCD_HSYNC */
0x11a1 /* MX28_PAD_LCD_RS__LCD_DOTCLK */
0x11b1 /* MX28_PAD_LCD_CS__LCD_ENABLE */
>;
fsl,drive-strength = <0>;
fsl,voltage = <1>;
fsl,pull-up = <0>;
};
};
lcdif@80030000 {
pinctrl-names = "default";
pinctrl-0 = <&lcdif_18bit_pins_cfa10049
&lcdif_pins_cfa10049>;
status = "okay";
};
};
apbx@80040000 {
pwm: pwm@80064000 {
pinctrl-names = "default", "default";
pinctrl-1 = <&pwm3_pins_b>;
status = "okay";
};
i2c1: i2c@8005a000 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins_a>;
......@@ -113,6 +164,19 @@ i2c@2 {
i2c@3 {
reg = <3>;
#address-cells = <1>;
#size-cells = <0>;
pca9555: pca9555@20 {
compatible = "nxp,pca9555";
interrupt-parent = <&gpio2>;
interrupts = <19 0x2>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x20>;
};
};
};
......@@ -153,4 +217,92 @@ mac0: ethernet@800f0000 {
status = "okay";
};
};
spi2 {
compatible = "spi-gpio";
pinctrl-names = "default";
pinctrl-0 = <&spi2_pins_cfa10049>;
status = "okay";
gpio-sck = <&gpio2 16 0>;
gpio-mosi = <&gpio2 17 0>;
gpio-miso = <&gpio2 18 0>;
cs-gpios = <&gpio3 23 0>;
num-chipselects = <1>;
#address-cells = <1>;
#size-cells = <0>;
hx8357: hx8357@0 {
compatible = "himax,hx8357b", "himax,hx8357";
reg = <0>;
spi-max-frequency = <100000>;
spi-cpol;
spi-cpha;
gpios-reset = <&gpio3 30 0>;
im-gpios = <&gpio5 4 0 &gpio5 5 0 &gpio5 6 0>;
};
};
spi3 {
compatible = "spi-gpio";
pinctrl-names = "default";
pinctrl-0 = <&spi3_pins_cfa10049>;
status = "okay";
gpio-sck = <&gpio0 24 0>;
gpio-mosi = <&gpio0 28 0>;
cs-gpios = <&gpio0 17 0 &gpio0 26 0 &gpio0 27 0>;
num-chipselects = <3>;
#address-cells = <1>;
#size-cells = <0>;
gpio5: gpio5@0 {
compatible = "fairchild,74hc595";
gpio-controller;
#gpio-cells = <2>;
reg = <0>;
registers-number = <2>;
spi-max-frequency = <100000>;
};
gpio6: gpio6@1 {
compatible = "fairchild,74hc595";
gpio-controller;
#gpio-cells = <2>;
reg = <1>;
registers-number = <4>;
spi-max-frequency = <100000>;
};
dac0: dh2228@2 {
compatible = "rohm,dh2228fv";
reg = <2>;
spi-max-frequency = <100000>;
};
};
gpio_keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
rotary_button {
label = "rotary_button";
gpios = <&gpio3 26 1>;
debounce-interval = <10>;
linux,code = <28>;
};
};
rotary {
compatible = "rotary-encoder";
gpios = <&gpio3 24 1>, <&gpio3 25 1>;
linux,axis = <1>; /* REL_Y */
rotary-encoder,relative-axis;
};
backlight {
compatible = "pwm-backlight";
pwms = <&pwm 3 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <6>;
};
};
arch/arm/boot/dts/imx28-m28evk.dts
View file @ a8f3740f
......@@ -177,6 +177,7 @@ rtc: rtc@68 {
lradc@80050000 {
status = "okay";
fsl,lradc-touchscreen-wires = <4>;
};
duart: serial@80074000 {
......
arch/arm/boot/dts/imx28.dtsi
View file @ a8f3740f
......@@ -502,6 +502,16 @@ pwm3_pins_a: pwm3@0 {
fsl,pull-up = <0>;
};
pwm3_pins_b: pwm3@1 {
reg = <1>;
fsl,pinmux-ids = <
0x3141 /* MX28_PAD_SAIF0_MCLK__PWM3 */
>;
fsl,drive-strength = <0>;
fsl,voltage = <1>;
fsl,pull-up = <0>;
};
pwm4_pins_a: pwm4@0 {
reg = <0>;
fsl,pinmux-ids = <
......
arch/arm/boot/dts/ste-nomadik-s8815.dts 0 → 100644
View file @ a8f3740f
/*
* Device Tree for the ST-Ericsson Nomadik S8815 board
* Produced by Calao Systems
*/
/dts-v1/;
/include/ "ste-nomadik-stn8815.dtsi"
/ {
model = "Calao Systems USB-S8815";
compatible = "calaosystems,usb-s8815";
chosen {
bootargs = "root=/dev/ram0 console=ttyAMA1,115200n8 earlyprintk";
};
/* Custom board node with GPIO pins to active etc */
usb-s8815 {
/* The S8815 is using this very GPIO pin for the SMSC91x IRQs */
ethernet-gpio {
gpios = <&gpio3 19 0x1>;
interrupts = <19 0x1>;
interrupt-parent = <&gpio3>;
};
/* This will bias the MMC/SD card detect line */
mmcsd-gpio {
gpios = <&gpio3 16 0x1>;
};
};
};
arch/arm/boot/dts/ste-nomadik-stn8815.dtsi 0 → 100644
View file @ a8f3740f
/*
* Device Tree for the ST-Ericsson Nomadik 8815 STn8815 SoC
*/
/include/ "skeleton.dtsi"
/ {
#address-cells = <1>;
#size-cells = <1>;
memory {
reg = <0x00000000 0x04000000>,
<0x08000000 0x04000000>;
};
L2: l2-cache {
compatible = "arm,l210-cache";
reg = <0x10210000 0x1000>;
interrupt-parent = <&vica>;
interrupts = <30>;
cache-unified;
cache-level = <2>;
};
mtu0 {
/* Nomadik system timer */
reg = <0x101e2000 0x1000>;
interrupt-parent = <&vica>;
interrupts = <4>;
};
mtu1 {
/* Secondary timer */
reg = <0x101e3000 0x1000>;
interrupt-parent = <&vica>;
interrupts = <5>;
};
gpio0: gpio@101e4000 {
compatible = "st,nomadik-gpio";
reg = <0x101e4000 0x80>;
interrupt-parent = <&vica>;
interrupts = <6>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
gpio-bank = <0>;
};
gpio1: gpio@101e5000 {
compatible = "st,nomadik-gpio";
reg = <0x101e5000 0x80>;
interrupt-parent = <&vica>;
interrupts = <7>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
gpio-bank = <1>;
};
gpio2: gpio@101e6000 {
compatible = "st,nomadik-gpio";
reg = <0x101e6000 0x80>;
interrupt-parent = <&vica>;
interrupts = <8>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
gpio-bank = <2>;
};
gpio3: gpio@101e7000 {
compatible = "st,nomadik-gpio";
reg = <0x101e7000 0x80>;
interrupt-parent = <&vica>;
interrupts = <9>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
gpio-bank = <3>;
};
pinctrl {
compatible = "stericsson,nmk-pinctrl-stn8815";
};
/* A NAND flash of 128 MiB */
fsmc: flash@40000000 {
compatible = "stericsson,fsmc-nand";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x10100000 0x1000>, /* FSMC Register*/
<0x40000000 0x2000>, /* NAND Base DATA */
<0x41000000 0x2000>, /* NAND Base ADDR */
<0x40800000 0x2000>; /* NAND Base CMD */
reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
status = "okay";
partition@0 {
label = "X-Loader(NAND)";
reg = <0x0 0x40000>;
};
partition@40000 {
label = "MemInit(NAND)";
reg = <0x40000 0x40000>;
};
partition@80000 {
label = "BootLoader(NAND)";
reg = <0x80000 0x200000>;
};
partition@280000 {
label = "Kernel zImage(NAND)";
reg = <0x280000 0x300000>;
};
partition@580000 {
label = "Root Filesystem(NAND)";
reg = <0x580000 0x1600000>;
};
partition@1b80000 {
label = "User Filesystem(NAND)";
reg = <0x1b80000 0x6480000>;
};
};
external-bus@34000000 {
compatible = "simple-bus";
reg = <0x34000000 0x1000000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x34000000 0x1000000>;
ethernet@300 {
compatible = "smsc,lan91c111";
reg = <0x300 0x0fd00>;
};
};
/* I2C0 connected to the STw4811 power management chip */
i2c0 {
compatible = "i2c-gpio";
gpios = <&gpio1 31 0>, /* sda */
<&gpio1 30 0>; /* scl */
#address-cells = <1>;
#size-cells = <0>;
stw4811@2d {
compatible = "st,stw4811";
reg = <0x2d>;
};
};
/* I2C1 connected to various sensors */
i2c1 {
compatible = "i2c-gpio";
gpios = <&gpio1 22 0>, /* sda */
<&gpio1 21 0>; /* scl */
#address-cells = <1>;
#size-cells = <0>;
camera@2d {
compatible = "st,camera";
reg = <0x10>;
};
stw5095@1a {
compatible = "st,stw5095";
reg = <0x1a>;
};
lis3lv02dl@1d {
compatible = "st,lis3lv02dl";
reg = <0x1d>;
};
};
/* I2C2 connected to the USB portions of the STw4811 only */
i2c2 {
compatible = "i2c-gpio";
gpios = <&gpio2 10 0>, /* sda */
<&gpio2 9 0>; /* scl */
#address-cells = <1>;
#size-cells = <0>;
stw4811@2d {
compatible = "st,stw4811-usb";
reg = <0x2d>;
};
};
amba {
compatible = "arm,amba-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
vica: intc@0x10140000 {
compatible = "arm,versatile-vic";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0x10140000 0x20>;
};
vicb: intc@0x10140020 {
compatible = "arm,versatile-vic";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0x10140020 0x20>;
};
uart0: uart@101fd000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x101fd000 0x1000>;
interrupt-parent = <&vica>;
interrupts = <12>;
};
uart1: uart@101fb000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x101fb000 0x1000>;
interrupt-parent = <&vica>;
interrupts = <17>;
};
uart2: uart@101f2000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x101f2000 0x1000>;
interrupt-parent = <&vica>;
interrupts = <28>;
status = "disabled";
};
rng: rng@101b0000 {
compatible = "arm,primecell";
reg = <0x101b0000 0x1000>;
};
rtc: rtc@101e8000 {
compatible = "arm,pl031", "arm,primecell";
reg = <0x101e8000 0x1000>;
interrupt-parent = <&vica>;
interrupts = <10>;
};
mmcsd: sdi@101f6000 {
compatible = "arm,pl18x", "arm,primecell";
reg = <0x101f6000 0x1000>;
interrupt-parent = <&vica>;
interrupts = <22>;
max-frequency = <48000000>;
bus-width = <4>;
mmc-cap-mmc-highspeed;
mmc-cap-sd-highspeed;
cd-gpios = <&gpio3 15 0x1>;
cd-inverted;
};
};
};
arch/arm/boot/dts/sun4i-a10-hackberry.dts 0 → 100644
View file @ a8f3740f
/*
* Copyright 2012 Maxime Ripard
*
* Maxime Ripard <maxime.ripard@free-electrons.com>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
/include/ "sun4i-a10.dtsi"
/ {
model = "Miniand Hackberry";
compatible = "miniand,hackberry", "allwinner,sun4i-a10";
chosen {
bootargs = "earlyprintk console=ttyS0,115200";
};
soc {
uart0: uart@01c28000 {
status = "okay";
};
};
};
arch/arm/boot/dts/tegra20-colibri-512.dtsi 0 → 100644
View file @ a8f3740f
This diff is collapsed.
arch/arm/boot/dts/tegra20-harmony.dts
View file @ a8f3740f
......@@ -3,7 +3,7 @@
/include/ "tegra20.dtsi"
/ {
model = "NVIDIA Tegra2 Harmony evaluation board";
model = "NVIDIA Tegra20 Harmony evaluation board";
compatible = "nvidia,harmony", "nvidia,tegra20";
memory {
......@@ -252,7 +252,6 @@ i2s@70002800 {
serial@70006300 {
status = "okay";
clock-frequency = <216000000>;
};
i2c@7000c000 {
......@@ -452,6 +451,123 @@ sdhci@c8000600 {
bus-width = <8>;
};
kbc {
status = "okay";
nvidia,debounce-delay-ms = <2>;
nvidia,repeat-delay-ms = <160>;
nvidia,kbc-row-pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
nvidia,kbc-col-pins = <16 17 18 19 20 21 22 23>;
linux,keymap = <0x00020011 /* KEY_W */
0x0003001F /* KEY_S */
0x0004001E /* KEY_A */
0x0005002C /* KEY_Z */
0x000701D0 /* KEY_FN */
0x0107008B /* KEY_MENU */
0x02060038 /* KEY_LEFTALT */
0x02070064 /* KEY_RIGHTALT */
0x03000006 /* KEY_5 */
0x03010005 /* KEY_4 */
0x03020013 /* KEY_R */
0x03030012 /* KEY_E */
0x03040021 /* KEY_F */
0x03050020 /* KEY_D */
0x0306002D /* KEY_X */
0x04000008 /* KEY_7 */
0x04010007 /* KEY_6 */
0x04020014 /* KEY_T */
0x04030023 /* KEY_H */
0x04040022 /* KEY_G */
0x0405002F /* KEY_V */
0x0406002E /* KEY_C */
0x04070039 /* KEY_SPACE */
0x0500000A /* KEY_9 */
0x05010009 /* KEY_8 */
0x05020016 /* KEY_U */
0x05030015 /* KEY_Y */
0x05040024 /* KEY_J */
0x05050031 /* KEY_N */
0x05060030 /* KEY_B */
0x0507002B /* KEY_BACKSLASH */
0x0600000C /* KEY_MINUS */
0x0601000B /* KEY_0 */
0x06020018 /* KEY_O */
0x06030017 /* KEY_I */
0x06040026 /* KEY_L */
0x06050025 /* KEY_K */
0x06060033 /* KEY_COMMA */
0x06070032 /* KEY_M */
0x0701000D /* KEY_EQUAL */
0x0702001B /* KEY_RIGHTBRACE */
0x0703001C /* KEY_ENTER */
0x0707008B /* KEY_MENU */
0x0804002A /* KEY_LEFTSHIFT */
0x08050036 /* KEY_RIGHTSHIFT */
0x0905001D /* KEY_LEFTCTRL */
0x09070061 /* KEY_RIGHTCTRL */
0x0B00001A /* KEY_LEFTBRACE */
0x0B010019 /* KEY_P */
0x0B020028 /* KEY_APOSTROPHE */
0x0B030027 /* KEY_SEMICOLON */
0x0B040035 /* KEY_SLASH */
0x0B050034 /* KEY_DOT */
0x0C000044 /* KEY_F10 */
0x0C010043 /* KEY_F9 */
0x0C02000E /* KEY_BACKSPACE */
0x0C030004 /* KEY_3 */
0x0C040003 /* KEY_2 */
0x0C050067 /* KEY_UP */
0x0C0600D2 /* KEY_PRINT */
0x0C070077 /* KEY_PAUSE */
0x0D00006E /* KEY_INSERT */
0x0D01006F /* KEY_DELETE */
0x0D030068 /* KEY_PAGEUP */
0x0D04006D /* KEY_PAGEDOWN */
0x0D05006A /* KEY_RIGHT */
0x0D06006C /* KEY_DOWN */
0x0D070069 /* KEY_LEFT */
0x0E000057 /* KEY_F11 */
0x0E010058 /* KEY_F12 */
0x0E020042 /* KEY_F8 */
0x0E030010 /* KEY_Q */
0x0E04003E /* KEY_F4 */
0x0E05003D /* KEY_F3 */
0x0E060002 /* KEY_1 */
0x0E070041 /* KEY_F7 */
0x0F000001 /* KEY_ESC */
0x0F010029 /* KEY_GRAVE */
0x0F02003F /* KEY_F5 */
0x0F03000F /* KEY_TAB */
0x0F04003B /* KEY_F1 */
0x0F05003C /* KEY_F2 */
0x0F06003A /* KEY_CAPSLOCK */
0x0F070040 /* KEY_F6 */
0x14000047 /* KEY_KP7 */
0x15000049 /* KEY_KP9 */
0x15010048 /* KEY_KP8 */
0x1502004B /* KEY_KP4 */
0x1504004F /* KEY_KP1 */
0x1601004E /* KEY_KPSLASH */
0x1602004D /* KEY_KP6 */
0x1603004C /* KEY_KP5 */
0x16040051 /* KEY_KP3 */
0x16050050 /* KEY_KP2 */
0x16070052 /* KEY_KP0 */
0x1B010037 /* KEY_KPASTERISK */
0x1B03004A /* KEY_KPMINUS */
0x1B04004E /* KEY_KPPLUS */
0x1B050053 /* KEY_KPDOT */
0x1C050073 /* KEY_VOLUMEUP */
0x1D030066 /* KEY_HOME */
0x1D04006B /* KEY_END */
0x1D0500E1 /* KEY_BRIGHTNESSUP */
0x1D060072 /* KEY_VOLUMEDOWN */
0x1D0700E0 /* KEY_BRIGHTNESSDOWN */
0x1E000045 /* KEY_NUMLOCK */
0x1E010046 /* KEY_SCROLLLOCK */
0x1E020071 /* KEY_MUTE */
0x1F0400D6>; /* KEY_QUESTION */
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
......
arch/arm/boot/dts/tegra20-iris-512.dts 0 → 100644
View file @ a8f3740f
/dts-v1/;
/include/ "tegra20-colibri-512.dtsi"
/ {
model = "Toradex Colibri T20 512MB on Iris";
compatible = "toradex,iris", "toradex,colibri_t20-512", "nvidia,tegra20";
host1x {
hdmi {
status = "okay";
};
};
pinmux {
state_default: pinmux {
hdint {
nvidia,tristate = <0>;
};
i2cddc {
nvidia,tristate = <0>;
};
sdio4 {
nvidia,tristate = <0>;
};
uarta {
nvidia,tristate = <0>;
};
uartd {
nvidia,tristate = <0>;
};
};
};
usb@c5000000 {
status = "okay";
dr_mode = "otg";
};
usb@c5008000 {
status = "okay";
};
serial@70006000 {
status = "okay";
};
serial@70006300 {
status = "okay";
};
i2c_ddc: i2c@7000c400 {
status = "okay";
};
sdhci@c8000600 {
status = "okay";
bus-width = <4>;
vmmc-supply = <&vcc_sd_reg>;
vqmmc-supply = <&vcc_sd_reg>;
};
regulators {
regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "usb_host_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-boot-on;
regulator-always-on;
gpio = <&gpio 178 0>;
};
vcc_sd_reg: regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "vcc_sd";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
};
};
arch/arm/boot/dts/tegra20-paz00.dts
View file @ a8f3740f
......@@ -10,6 +10,18 @@ memory {
reg = <0x00000000 0x20000000>;
};
host1x {
hdmi {
status = "okay";
vdd-supply = <&hdmi_vdd_reg>;
pll-supply = <&hdmi_pll_reg>;
nvidia,ddc-i2c-bus = <&hdmi_ddc>;
nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
};
};
pinmux {
pinctrl-names = "default";
pinctrl-0 = <&state_default>;
......@@ -232,12 +244,10 @@ i2s@70002800 {
serial@70006000 {
status = "okay";
clock-frequency = <216000000>;
};
serial@70006200 {
status = "okay";
clock-frequency = <216000000>;
};
i2c@7000c000 {
......@@ -252,9 +262,9 @@ alc5632: alc5632@1e {
};
};
i2c@7000c400 {
hdmi_ddc: i2c@7000c400 {
status = "okay";
clock-frequency = <400000>;
clock-frequency = <100000>;
};
nvec {
......@@ -369,13 +379,13 @@ ldo6 {
regulator-max-microvolt = <1800000>;
};
ldo7 {
hdmi_vdd_reg: ldo7 {
regulator-name = "+3.3vs_ldo7,avdd_hdmi";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
ldo8 {
hdmi_pll_reg: ldo8 {
regulator-name = "+1.8vs_ldo8,avdd_hdmi_pll";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
......
arch/arm/boot/dts/tegra20-seaboard.dts
View file @ a8f3740f
......@@ -10,6 +10,18 @@ memory {
reg = <0x00000000 0x40000000>;
};
host1x {
hdmi {
status = "okay";
vdd-supply = <&hdmi_vdd_reg>;
pll-supply = <&hdmi_pll_reg>;
nvidia,ddc-i2c-bus = <&hdmi_ddc>;
nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
};
};
pinmux {
pinctrl-names = "default";
pinctrl-0 = <&state_default>;
......@@ -291,7 +303,6 @@ i2s@70002800 {
serial@70006300 {
status = "okay";
clock-frequency = <216000000>;
};
i2c@7000c000 {
......@@ -345,7 +356,7 @@ i2cmux {
pinctrl-1 = <&state_i2cmux_pta>;
pinctrl-2 = <&state_i2cmux_idle>;
i2c@0 {
hdmi_ddc: i2c@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
......@@ -463,13 +474,13 @@ ldo6 {
regulator-max-microvolt = <1800000>;
};
ldo7 {
hdmi_vdd_reg: ldo7 {
regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
ldo8 {
hdmi_pll_reg: ldo8 {
regulator-name = "vdd_ldo8,avdd_hdmi_pll";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
......@@ -604,6 +615,145 @@ lid {
};
};
kbc {
status = "okay";
nvidia,debounce-delay-ms = <32>;
nvidia,repeat-delay-ms = <160>;
nvidia,ghost-filter;
nvidia,kbc-row-pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
nvidia,kbc-col-pins = <16 17 18 19 20 21 22 23>;
linux,keymap = <0x00020011 /* KEY_W */
0x0003001F /* KEY_S */
0x0004001E /* KEY_A */
0x0005002C /* KEY_Z */
0x000701d0 /* KEY_FN */
0x0107007D /* KEY_LEFTMETA */
0x02060064 /* KEY_RIGHTALT */
0x02070038 /* KEY_LEFTALT */
0x03000006 /* KEY_5 */
0x03010005 /* KEY_4 */
0x03020013 /* KEY_R */
0x03030012 /* KEY_E */
0x03040021 /* KEY_F */
0x03050020 /* KEY_D */
0x0306002D /* KEY_X */
0x04000008 /* KEY_7 */
0x04010007 /* KEY_6 */
0x04020014 /* KEY_T */
0x04030023 /* KEY_H */
0x04040022 /* KEY_G */
0x0405002F /* KEY_V */
0x0406002E /* KEY_C */
0x04070039 /* KEY_SPACE */
0x0500000A /* KEY_9 */
0x05010009 /* KEY_8 */
0x05020016 /* KEY_U */
0x05030015 /* KEY_Y */
0x05040024 /* KEY_J */
0x05050031 /* KEY_N */
0x05060030 /* KEY_B */
0x0507002B /* KEY_BACKSLASH */
0x0600000C /* KEY_MINUS */
0x0601000B /* KEY_0 */
0x06020018 /* KEY_O */
0x06030017 /* KEY_I */
0x06040026 /* KEY_L */
0x06050025 /* KEY_K */
0x06060033 /* KEY_COMMA */
0x06070032 /* KEY_M */
0x0701000D /* KEY_EQUAL */
0x0702001B /* KEY_RIGHTBRACE */
0x0703001C /* KEY_ENTER */
0x0707008B /* KEY_MENU */
0x08040036 /* KEY_RIGHTSHIFT */
0x0805002A /* KEY_LEFTSHIFT */
0x09050061 /* KEY_RIGHTCTRL */
0x0907001D /* KEY_LEFTCTRL */
0x0B00001A /* KEY_LEFTBRACE */
0x0B010019 /* KEY_P */
0x0B020028 /* KEY_APOSTROPHE */
0x0B030027 /* KEY_SEMICOLON */
0x0B040035 /* KEY_SLASH */
0x0B050034 /* KEY_DOT */
0x0C000044 /* KEY_F10 */
0x0C010043 /* KEY_F9 */
0x0C02000E /* KEY_BACKSPACE */
0x0C030004 /* KEY_3 */
0x0C040003 /* KEY_2 */
0x0C050067 /* KEY_UP */
0x0C0600D2 /* KEY_PRINT */
0x0C070077 /* KEY_PAUSE */
0x0D00006E /* KEY_INSERT */
0x0D01006F /* KEY_DELETE */
0x0D030068 /* KEY_PAGEUP */
0x0D04006D /* KEY_PAGEDOWN */
0x0D05006A /* KEY_RIGHT */
0x0D06006C /* KEY_DOWN */
0x0D070069 /* KEY_LEFT */
0x0E000057 /* KEY_F11 */
0x0E010058 /* KEY_F12 */
0x0E020042 /* KEY_F8 */
0x0E030010 /* KEY_Q */
0x0E04003E /* KEY_F4 */
0x0E05003D /* KEY_F3 */
0x0E060002 /* KEY_1 */
0x0E070041 /* KEY_F7 */
0x0F000001 /* KEY_ESC */
0x0F010029 /* KEY_GRAVE */
0x0F02003F /* KEY_F5 */
0x0F03000F /* KEY_TAB */
0x0F04003B /* KEY_F1 */
0x0F05003C /* KEY_F2 */
0x0F06003A /* KEY_CAPSLOCK */
0x0F070040 /* KEY_F6 */
/* Software Handled Function Keys */
0x14000047 /* KEY_KP7 */
0x15000049 /* KEY_KP9 */
0x15010048 /* KEY_KP8 */
0x1502004B /* KEY_KP4 */
0x1504004F /* KEY_KP1 */
0x1601004E /* KEY_KPSLASH */
0x1602004D /* KEY_KP6 */
0x1603004C /* KEY_KP5 */
0x16040051 /* KEY_KP3 */
0x16050050 /* KEY_KP2 */
0x16070052 /* KEY_KP0 */
0x1B010037 /* KEY_KPASTERISK */
0x1B03004A /* KEY_KPMINUS */
0x1B04004E /* KEY_KPPLUS */
0x1B050053 /* KEY_KPDOT */
0x1C050073 /* KEY_VOLUMEUP */
0x1D030066 /* KEY_HOME */
0x1D04006B /* KEY_END */
0x1D0500E0 /* KEY_BRIGHTNESSDOWN */
0x1D060072 /* KEY_VOLUMEDOWN */
0x1D0700E1 /* KEY_BRIGHTNESSUP */
0x1E000045 /* KEY_NUMLOCK */
0x1E010046 /* KEY_SCROLLLOCK */
0x1E020071 /* KEY_MUTE */
0x1F04008A>; /* KEY_HELP */
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
......
arch/arm/boot/dts/tegra20-tamonten.dtsi
View file @ a8f3740f
......@@ -276,7 +276,6 @@ i2s@70002800 {
};
serial@70006300 {
clock-frequency = <216000000>;
status = "okay";
};
......
arch/arm/boot/dts/tegra20-trimslice.dts
View file @ a8f3740f
......@@ -249,6 +249,11 @@ conf_ld17_0 {
"ld23_22";
nvidia,pull = <1>;
};
conf_spif {
nvidia,pins = "spif";
nvidia,pull = <1>;
nvidia,tristate = <0>;
};
};
};
......@@ -258,7 +263,6 @@ i2s@70002800 {
serial@70006000 {
status = "okay";
clock-frequency = <216000000>;
};
dvi_ddc: i2c@7000c000 {
......@@ -326,6 +330,11 @@ sdhci@c8000600 {
bus-width = <4>;
};
poweroff {
compatible = "gpio-poweroff";
gpios = <&gpio 191 1>; /* gpio PX7, active low */
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
......
arch/arm/boot/dts/tegra20-ventana.dts
View file @ a8f3740f
......@@ -3,13 +3,25 @@
/include/ "tegra20.dtsi"
/ {
model = "NVIDIA Tegra2 Ventana evaluation board";
model = "NVIDIA Tegra20 Ventana evaluation board";
compatible = "nvidia,ventana", "nvidia,tegra20";
memory {
reg = <0x00000000 0x40000000>;
};
host1x {
hdmi {
status = "okay";
vdd-supply = <&hdmi_vdd_reg>;
pll-supply = <&hdmi_pll_reg>;
nvidia,ddc-i2c-bus = <&hdmi_ddc>;
nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
};
};
pinmux {
pinctrl-names = "default";
pinctrl-0 = <&state_default>;
......@@ -288,7 +300,6 @@ i2s@70002800 {
serial@70006300 {
status = "okay";
clock-frequency = <216000000>;
};
i2c@7000c000 {
......@@ -320,7 +331,7 @@ isl29018@44 {
i2c@7000c400 {
status = "okay";
clock-frequency = <400000>;
clock-frequency = <100000>;
};
i2cmux {
......@@ -335,7 +346,7 @@ i2cmux {
pinctrl-1 = <&state_i2cmux_pta>;
pinctrl-2 = <&state_i2cmux_idle>;
i2c@0 {
hdmi_ddc: i2c@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
......@@ -446,13 +457,13 @@ ldo6 {
regulator-max-microvolt = <1800000>;
};
ldo7 {
hdmi_vdd_reg: ldo7 {
regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
ldo8 {
hdmi_pll_reg: ldo8 {
regulator-name = "vdd_ldo8,avdd_hdmi_pll";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
......
arch/arm/boot/dts/tegra20-whistler.dts
View file @ a8f3740f
......@@ -3,7 +3,7 @@
/include/ "tegra20.dtsi"
/ {
model = "NVIDIA Tegra2 Whistler evaluation board";
model = "NVIDIA Tegra20 Whistler evaluation board";
compatible = "nvidia,whistler", "nvidia,tegra20";
memory {
......@@ -255,7 +255,6 @@ i2s@70002800 {
serial@70006000 {
status = "okay";
clock-frequency = <216000000>;
};
hdmi_ddc: i2c@7000c400 {
......@@ -520,6 +519,18 @@ sdhci@c8000600 {
bus-width = <8>;
};
kbc {
status = "okay";
nvidia,debounce-delay-ms = <20>;
nvidia,repeat-delay-ms = <160>;
nvidia,kbc-row-pins = <0 1 2>;
nvidia,kbc-col-pins = <16 17>;
linux,keymap = <0x00000074 /* KEY_POWER */
0x01000066 /* KEY_HOME */
0x0101009E /* KEY_BACK */
0x0201008B>; /* KEY_MENU */
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
......
arch/arm/boot/dts/tegra20.dtsi
View file @ a8f3740f
......@@ -4,6 +4,14 @@ / {
compatible = "nvidia,tegra20";
interrupt-parent = <&intc>;
aliases {
serial0 = &uarta;
serial1 = &uartb;
serial2 = &uartc;
serial3 = &uartd;
serial4 = &uarte;
};
host1x {
compatible = "nvidia,tegra20-host1x", "simple-bus";
reg = <0x50000000 0x00024000>;
......@@ -112,15 +120,6 @@ timer@50004600 {
interrupts = <1 13 0x304>;
};
cache-controller@50043000 {
compatible = "arm,pl310-cache";
reg = <0x50043000 0x1000>;
arm,data-latency = <5 5 2>;
arm,tag-latency = <4 4 2>;
cache-unified;
cache-level = <2>;
};
intc: interrupt-controller {
compatible = "arm,cortex-a9-gic";
reg = <0x50041000 0x1000
......@@ -129,6 +128,15 @@ intc: interrupt-controller {
#interrupt-cells = <3>;
};
cache-controller {
compatible = "arm,pl310-cache";
reg = <0x50043000 0x1000>;
arm,data-latency = <5 5 2>;
arm,tag-latency = <4 4 2>;
cache-unified;
cache-level = <2>;
};
timer@60005000 {
compatible = "nvidia,tegra20-timer";
reg = <0x60005000 0x60>;
......@@ -199,6 +207,15 @@ das {
compatible = "nvidia,tegra20-das";
reg = <0x70000c00 0x80>;
};
tegra_ac97: ac97 {
compatible = "nvidia,tegra20-ac97";
reg = <0x70002000 0x200>;
interrupts = <0 81 0x04>;
nvidia,dma-request-selector = <&apbdma 12>;
clocks = <&tegra_car 3>;
status = "disabled";
};
tegra_i2s1: i2s@70002800 {
compatible = "nvidia,tegra20-i2s";
......@@ -218,47 +235,59 @@ tegra_i2s2: i2s@70002a00 {
status = "disabled";
};
serial@70006000 {
/*
* There are two serial driver i.e. 8250 based simple serial
* driver and APB DMA based serial driver for higher baudrate
* and performace. To enable the 8250 based driver, the compatible
* is "nvidia,tegra20-uart" and to enable the APB DMA based serial
* driver, the comptible is "nvidia,tegra20-hsuart".
*/
uarta: serial@70006000 {
compatible = "nvidia,tegra20-uart";
reg = <0x70006000 0x40>;
reg-shift = <2>;
interrupts = <0 36 0x04>;
nvidia,dma-request-selector = <&apbdma 8>;
clocks = <&tegra_car 6>;
status = "disabled";
};
serial@70006040 {
uartb: serial@70006040 {
compatible = "nvidia,tegra20-uart";
reg = <0x70006040 0x40>;
reg-shift = <2>;
interrupts = <0 37 0x04>;
nvidia,dma-request-selector = <&apbdma 9>;
clocks = <&tegra_car 96>;
status = "disabled";
};
serial@70006200 {
uartc: serial@70006200 {
compatible = "nvidia,tegra20-uart";
reg = <0x70006200 0x100>;
reg-shift = <2>;
interrupts = <0 46 0x04>;
nvidia,dma-request-selector = <&apbdma 10>;
clocks = <&tegra_car 55>;
status = "disabled";
};
serial@70006300 {
uartd: serial@70006300 {
compatible = "nvidia,tegra20-uart";
reg = <0x70006300 0x100>;
reg-shift = <2>;
interrupts = <0 90 0x04>;
nvidia,dma-request-selector = <&apbdma 19>;
clocks = <&tegra_car 65>;
status = "disabled";
};
serial@70006400 {
uarte: serial@70006400 {
compatible = "nvidia,tegra20-uart";
reg = <0x70006400 0x100>;
reg-shift = <2>;
interrupts = <0 91 0x04>;
nvidia,dma-request-selector = <&apbdma 20>;
clocks = <&tegra_car 66>;
status = "disabled";
};
......@@ -375,6 +404,14 @@ spi@7000da00 {
status = "disabled";
};
kbc {
compatible = "nvidia,tegra20-kbc";
reg = <0x7000e200 0x100>;
interrupts = <0 85 0x04>;
clocks = <&tegra_car 36>;
status = "disabled";
};
pmc {
compatible = "nvidia,tegra20-pmc";
reg = <0x7000e400 0x400>;
......@@ -387,7 +424,7 @@ memory-controller@7000f000 {
interrupts = <0 77 0x04>;
};
gart {
iommu {
compatible = "nvidia,tegra20-gart";
reg = <0x7000f024 0x00000018 /* controller registers */
0x58000000 0x02000000>; /* GART aperture */
......
arch/arm/boot/dts/tegra30-beaver.dts 0 → 100644
View file @ a8f3740f
/dts-v1/;
/include/ "tegra30.dtsi"
/ {
model = "NVIDIA Tegra30 Beaver evaluation board";
compatible = "nvidia,beaver", "nvidia,tegra30";
memory {
reg = <0x80000000 0x80000000>;
};
pinmux {
pinctrl-names = "default";
pinctrl-0 = <&state_default>;
state_default: pinmux {
sdmmc1_clk_pz0 {
nvidia,pins = "sdmmc1_clk_pz0";
nvidia,function = "sdmmc1";
nvidia,pull = <0>;
nvidia,tristate = <0>;
};
sdmmc1_cmd_pz1 {
nvidia,pins = "sdmmc1_cmd_pz1",
"sdmmc1_dat0_py7",
"sdmmc1_dat1_py6",
"sdmmc1_dat2_py5",
"sdmmc1_dat3_py4";
nvidia,function = "sdmmc1";
nvidia,pull = <2>;
nvidia,tristate = <0>;
};
sdmmc3_clk_pa6 {
nvidia,pins = "sdmmc3_clk_pa6";
nvidia,function = "sdmmc3";
nvidia,pull = <0>;
nvidia,tristate = <0>;
};
sdmmc3_cmd_pa7 {
nvidia,pins = "sdmmc3_cmd_pa7",
"sdmmc3_dat0_pb7",
"sdmmc3_dat1_pb6",
"sdmmc3_dat2_pb5",
"sdmmc3_dat3_pb4";
nvidia,function = "sdmmc3";
nvidia,pull = <2>;
nvidia,tristate = <0>;
};
sdmmc4_clk_pcc4 {
nvidia,pins = "sdmmc4_clk_pcc4",
"sdmmc4_rst_n_pcc3";
nvidia,function = "sdmmc4";
nvidia,pull = <0>;
nvidia,tristate = <0>;
};
sdmmc4_dat0_paa0 {
nvidia,pins = "sdmmc4_dat0_paa0",
"sdmmc4_dat1_paa1",
"sdmmc4_dat2_paa2",
"sdmmc4_dat3_paa3",
"sdmmc4_dat4_paa4",
"sdmmc4_dat5_paa5",
"sdmmc4_dat6_paa6",
"sdmmc4_dat7_paa7";
nvidia,function = "sdmmc4";
nvidia,pull = <2>;
nvidia,tristate = <0>;
};
dap2_fs_pa2 {
nvidia,pins = "dap2_fs_pa2",
"dap2_sclk_pa3",
"dap2_din_pa4",
"dap2_dout_pa5";
nvidia,function = "i2s1";
nvidia,pull = <0>;
nvidia,tristate = <0>;
};
sdio3 {
nvidia,pins = "drive_sdio3";
nvidia,high-speed-mode = <0>;
nvidia,schmitt = <0>;
nvidia,pull-down-strength = <46>;
nvidia,pull-up-strength = <42>;
nvidia,slew-rate-rising = <1>;
nvidia,slew-rate-falling = <1>;
};
};
};
serial@70006000 {
status = "okay";
};
i2c@7000c000 {
status = "okay";
clock-frequency = <100000>;
};
i2c@7000c400 {
status = "okay";
clock-frequency = <100000>;
};
i2c@7000c500 {
status = "okay";
clock-frequency = <100000>;
};
i2c@7000c700 {
status = "okay";
clock-frequency = <100000>;
};
i2c@7000d000 {
status = "okay";
clock-frequency = <100000>;
tps62361 {
compatible = "ti,tps62361";
reg = <0x60>;
regulator-name = "tps62361-vout";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1500000>;
regulator-boot-on;
regulator-always-on;
ti,vsel0-state-high;
ti,vsel1-state-high;
};
pmic: tps65911@2d {
compatible = "ti,tps65911";
reg = <0x2d>;
interrupts = <0 86 0x4>;
#interrupt-cells = <2>;
interrupt-controller;
ti,system-power-controller;
#gpio-cells = <2>;
gpio-controller;
vcc1-supply = <&vdd_5v_in_reg>;
vcc2-supply = <&vdd_5v_in_reg>;
vcc3-supply = <&vio_reg>;
vcc4-supply = <&vdd_5v_in_reg>;
vcc5-supply = <&vdd_5v_in_reg>;
vcc6-supply = <&vdd2_reg>;
vcc7-supply = <&vdd_5v_in_reg>;
vccio-supply = <&vdd_5v_in_reg>;
regulators {
#address-cells = <1>;
#size-cells = <0>;
vdd1_reg: vdd1 {
regulator-name = "vddio_ddr_1v2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
};
vdd2_reg: vdd2 {
regulator-name = "vdd_1v5_gen";
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-always-on;
};
vddctrl_reg: vddctrl {
regulator-name = "vdd_cpu,vdd_sys";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
};
vio_reg: vio {
regulator-name = "vdd_1v8_gen";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
ldo1_reg: ldo1 {
regulator-name = "vdd_pexa,vdd_pexb";
regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1050000>;
};
ldo2_reg: ldo2 {
regulator-name = "vdd_sata,avdd_plle";
regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1050000>;
};
/* LDO3 is not connected to anything */
ldo4_reg: ldo4 {
regulator-name = "vdd_rtc";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
};
ldo5_reg: ldo5 {
regulator-name = "vddio_sdmmc,avdd_vdac";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
ldo6_reg: ldo6 {
regulator-name = "avdd_dsi_csi,pwrdet_mipi";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
};
ldo7_reg: ldo7 {
regulator-name = "vdd_pllm,x,u,a_p_c_s";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
};
ldo8_reg: ldo8 {
regulator-name = "vdd_ddr_hs";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
};
};
};
};
spi@7000da00 {
status = "okay";
spi-max-frequency = <25000000>;
spi-flash@1 {
compatible = "winbond,w25q32";
reg = <1>;
spi-max-frequency = <20000000>;
};
};
ahub {
i2s@70080400 {
status = "okay";
};
};
pmc {
status = "okay";
nvidia,invert-interrupt;
};
sdhci@78000000 {
status = "okay";
cd-gpios = <&gpio 69 0>; /* gpio PI5 */
wp-gpios = <&gpio 155 0>; /* gpio PT3 */
power-gpios = <&gpio 31 0>; /* gpio PD7 */
bus-width = <4>;
};
sdhci@78000600 {
status = "okay";
bus-width = <8>;
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
vdd_5v_in_reg: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "vdd_5v_in";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
chargepump_5v_reg: regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "chargepump_5v";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-boot-on;
regulator-always-on;
enable-active-high;
gpio = <&pmic 0 0>; /* PMIC TPS65911 GPIO0 */
};
ddr_reg: regulator@2 {
compatible = "regulator-fixed";
reg = <2>;
regulator-name = "vdd_ddr";
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-always-on;
regulator-boot-on;
enable-active-high;
gpio = <&pmic 7 0>; /* PMIC TPS65911 GPIO7 */
vin-supply = <&vdd_5v_in_reg>;
};
vdd_5v_sata_reg: regulator@3 {
compatible = "regulator-fixed";
reg = <3>;
regulator-name = "vdd_5v_sata";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
regulator-boot-on;
enable-active-high;
gpio = <&gpio 30 0>; /* gpio PD6 */
vin-supply = <&vdd_5v_in_reg>;
};
usb1_vbus_reg: regulator@4 {
compatible = "regulator-fixed";
reg = <4>;
regulator-name = "usb1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&gpio 68 0>; /* GPIO PI4 */
gpio-open-drain;
vin-supply = <&vdd_5v_in_reg>;
};
usb3_vbus_reg: regulator@5 {
compatible = "regulator-fixed";
reg = <5>;
regulator-name = "usb3_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&gpio 63 0>; /* GPIO PH7 */
gpio-open-drain;
vin-supply = <&vdd_5v_in_reg>;
};
sys_3v3_reg: regulator@6 {
compatible = "regulator-fixed";
reg = <6>;
regulator-name = "sys_3v3,vdd_3v3_alw";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
enable-active-high;
gpio = <&pmic 6 0>; /* PMIC TPS65911 GPIO6 */
vin-supply = <&vdd_5v_in_reg>;
};
sys_3v3_pexs_reg: regulator@7 {
compatible = "regulator-fixed";
reg = <7>;
regulator-name = "sys_3v3_pexs";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
enable-active-high;
gpio = <&gpio 95 0>; /* gpio PL7 */
vin-supply = <&sys_3v3_reg>;
};
};
};
arch/arm/boot/dts/tegra30-cardhu.dtsi
View file @ a8f3740f
......@@ -106,12 +106,25 @@ sdio3 {
nvidia,slew-rate-rising = <1>;
nvidia,slew-rate-falling = <1>;
};
uart3_txd_pw6 {
nvidia,pins = "uart3_txd_pw6",
"uart3_cts_n_pa1",
"uart3_rts_n_pc0",
"uart3_rxd_pw7";
nvidia,function = "uartc";
nvidia,pull = <0>;
nvidia,tristate = <0>;
};
};
};
serial@70006000 {
status = "okay";
clock-frequency = <408000000>;
};
serial@70006200 {
compatible = "nvidia,tegra30-hsuart";
status = "okay";
};
i2c@7000c000 {
......
arch/arm/boot/dts/tegra30.dtsi
View file @ a8f3740f
......@@ -4,6 +4,14 @@ / {
compatible = "nvidia,tegra30";
interrupt-parent = <&intc>;
aliases {
serial0 = &uarta;
serial1 = &uartb;
serial2 = &uartc;
serial3 = &uartd;
serial4 = &uarte;
};
host1x {
compatible = "nvidia,tegra30-host1x", "simple-bus";
reg = <0x50000000 0x00024000>;
......@@ -113,15 +121,6 @@ timer@50004600 {
interrupts = <1 13 0xf04>;
};
cache-controller@50043000 {
compatible = "arm,pl310-cache";
reg = <0x50043000 0x1000>;
arm,data-latency = <6 6 2>;
arm,tag-latency = <5 5 2>;
cache-unified;
cache-level = <2>;
};
intc: interrupt-controller {
compatible = "arm,cortex-a9-gic";
reg = <0x50041000 0x1000
......@@ -130,6 +129,15 @@ intc: interrupt-controller {
#interrupt-cells = <3>;
};
cache-controller {
compatible = "arm,pl310-cache";
reg = <0x50043000 0x1000>;
arm,data-latency = <6 6 2>;
arm,tag-latency = <5 5 2>;
cache-unified;
cache-level = <2>;
};
timer@60005000 {
compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
reg = <0x60005000 0x400>;
......@@ -191,7 +199,7 @@ ahb: ahb {
};
gpio: gpio {
compatible = "nvidia,tegra30-gpio", "nvidia,tegra20-gpio";
compatible = "nvidia,tegra30-gpio";
reg = <0x6000d000 0x1000>;
interrupts = <0 32 0x04
0 33 0x04
......@@ -213,47 +221,60 @@ pinmux: pinmux {
0x70003000 0x3e4>; /* Mux registers */
};
serial@70006000 {
/*
* There are two serial driver i.e. 8250 based simple serial
* driver and APB DMA based serial driver for higher baudrate
* and performace. To enable the 8250 based driver, the compatible
* is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable
* the APB DMA based serial driver, the comptible is
* "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
*/
uarta: serial@70006000 {
compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
reg = <0x70006000 0x40>;
reg-shift = <2>;
interrupts = <0 36 0x04>;
nvidia,dma-request-selector = <&apbdma 8>;
clocks = <&tegra_car 6>;
status = "disabled";
};
serial@70006040 {
uartb: serial@70006040 {
compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
reg = <0x70006040 0x40>;
reg-shift = <2>;
interrupts = <0 37 0x04>;
nvidia,dma-request-selector = <&apbdma 9>;
clocks = <&tegra_car 160>;
status = "disabled";
};
serial@70006200 {
uartc: serial@70006200 {
compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
reg = <0x70006200 0x100>;
reg-shift = <2>;
interrupts = <0 46 0x04>;
nvidia,dma-request-selector = <&apbdma 10>;
clocks = <&tegra_car 55>;
status = "disabled";
};
serial@70006300 {
uartd: serial@70006300 {
compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
reg = <0x70006300 0x100>;
reg-shift = <2>;
interrupts = <0 90 0x04>;
nvidia,dma-request-selector = <&apbdma 19>;
clocks = <&tegra_car 65>;
status = "disabled";
};
serial@70006400 {
uarte: serial@70006400 {
compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
reg = <0x70006400 0x100>;
reg-shift = <2>;
interrupts = <0 91 0x04>;
nvidia,dma-request-selector = <&apbdma 20>;
clocks = <&tegra_car 66>;
status = "disabled";
};
......@@ -392,6 +413,14 @@ spi@7000de00 {
status = "disabled";
};
kbc {
compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
reg = <0x7000e200 0x100>;
interrupts = <0 85 0x04>;
clocks = <&tegra_car 36>;
status = "disabled";
};
pmc {
compatible = "nvidia,tegra20-pmc", "nvidia,tegra30-pmc";
reg = <0x7000e400 0x400>;
......@@ -406,7 +435,7 @@ memory-controller {
interrupts = <0 77 0x04>;
};
smmu {
iommu {
compatible = "nvidia,tegra30-smmu";
reg = <0x7000f010 0x02c
0x7000f1f0 0x010
......
arch/arm/configs/da8xx_omapl_defconfig
View file @ a8f3740f
......@@ -84,6 +84,7 @@ CONFIG_SERIAL_OF_PLATFORM=y
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_DAVINCI=y
CONFIG_PINCTRL_SINGLE=y
# CONFIG_HWMON is not set
CONFIG_WATCHDOG=y
CONFIG_REGULATOR=y
......
arch/arm/mach-at91/at91rm9200.c
View file @ a8f3740f
......@@ -210,6 +210,8 @@ static struct clk_lookup periph_clocks_lookups[] = {
CLKDEV_CON_DEV_ID("t0_clk", "fffa4000.timer", &tc3_clk),
CLKDEV_CON_DEV_ID("t1_clk", "fffa4000.timer", &tc4_clk),
CLKDEV_CON_DEV_ID("t2_clk", "fffa4000.timer", &tc5_clk),
CLKDEV_CON_DEV_ID("mci_clk", "fffb4000.mmc", &mmc_clk),
CLKDEV_CON_DEV_ID("emac_clk", "fffbc000.ethernet", &ether_clk),
CLKDEV_CON_DEV_ID("hclk", "300000.ohci", &ohci_clk),
CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioA_clk),
CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioB_clk),
......
arch/arm/mach-davinci/Kconfig
View file @ a8f3740f
......@@ -62,6 +62,7 @@ config MACH_DA8XX_DT
bool "Support DA8XX platforms using device tree"
default y
depends on ARCH_DAVINCI_DA8XX
select PINCTRL
help
Say y here to include support for TI DaVinci DA850 based using
Flattened Device Tree. More information at Documentation/devicetree
......
arch/arm/mach-davinci/da8xx-dt.c
View file @ a8f3740f
......@@ -37,11 +37,18 @@ static void __init da8xx_init_irq(void)
of_irq_init(da8xx_irq_match);
}
struct of_dev_auxdata da850_auxdata_lookup[] __initdata = {
OF_DEV_AUXDATA("ti,davinci-i2c", 0x01c22000, "i2c_davinci.1", NULL),
OF_DEV_AUXDATA("ti,davinci-wdt", 0x01c21000, "watchdog", NULL),
{}
};
#ifdef CONFIG_ARCH_DAVINCI_DA850
static void __init da850_init_machine(void)
{
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
of_platform_populate(NULL, of_default_bus_match_table,
da850_auxdata_lookup, NULL);
da8xx_uart_clk_enable();
}
......
arch/arm/mach-davinci/devices-da8xx.c
View file @ a8f3740f
......@@ -359,7 +359,7 @@ static struct resource da8xx_watchdog_resources[] = {
},
};
struct platform_device da8xx_wdt_device = {
static struct platform_device da8xx_wdt_device = {
.name = "watchdog",
.id = -1,
.num_resources = ARRAY_SIZE(da8xx_watchdog_resources),
......@@ -368,7 +368,15 @@ struct platform_device da8xx_wdt_device = {
void da8xx_restart(char mode, const char *cmd)
{
davinci_watchdog_reset(&da8xx_wdt_device);
struct device *dev;
dev = bus_find_device_by_name(&platform_bus_type, NULL, "watchdog");
if (!dev) {
pr_err("%s: failed to find watchdog device\n", __func__);
return;
}
davinci_watchdog_reset(to_platform_device(dev));
}
int __init da8xx_register_watchdog(void)
......
arch/arm/mach-davinci/include/mach/da8xx.h
View file @ a8f3740f
......@@ -110,7 +110,6 @@ extern struct emac_platform_data da8xx_emac_pdata;
extern struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata;
extern struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata;
extern struct platform_device da8xx_wdt_device;
extern const short da830_emif25_pins[];
extern const short da830_spi0_pins[];
......
arch/arm/mach-mxs/mach-mxs.c
View file @ a8f3740f
......@@ -119,6 +119,23 @@ static struct fb_videomode apf28dev_video_modes[] = {
},
};
static struct fb_videomode cfa10049_video_modes[] = {
{
.name = "Himax HX8357-B",
.refresh = 60,
.xres = 320,
.yres = 480,
.pixclock = 108506, /* picosecond (9.216 MHz) */
.left_margin = 2,
.right_margin = 2,
.upper_margin = 2,
.lower_margin = 2,
.hsync_len = 15,
.vsync_len = 15,
.sync = FB_SYNC_DATA_ENABLE_HIGH_ACT
},
};
static struct mxsfb_platform_data mxsfb_pdata __initdata;
/*
......@@ -387,6 +404,17 @@ static void __init cfa10049_init(void)
update_fec_mac_prop(OUI_CRYSTALFONTZ);
}
static void __init cfa10037_init(void)
{
enable_clk_enet_out();
update_fec_mac_prop(OUI_CRYSTALFONTZ);
mxsfb_pdata.mode_list = cfa10049_video_modes;
mxsfb_pdata.mode_count = ARRAY_SIZE(cfa10049_video_modes);
mxsfb_pdata.default_bpp = 32;
mxsfb_pdata.ld_intf_width = STMLCDIF_18BIT;
}
static void __init apf28_init(void)
{
enable_clk_enet_out();
......@@ -407,6 +435,8 @@ static void __init mxs_machine_init(void)
m28evk_init();
else if (of_machine_is_compatible("bluegiga,apx4devkit"))
apx4devkit_init();
else if (of_machine_is_compatible("crystalfontz,cfa10037"))
cfa10037_init();
else if (of_machine_is_compatible("crystalfontz,cfa10049"))
cfa10049_init();
else if (of_machine_is_compatible("armadeus,imx28-apf28"))
......
arch/arm/mach-nomadik/Kconfig
View file @ a8f3740f
......@@ -4,19 +4,13 @@ menu "Nomadik boards"
config MACH_NOMADIK_8815NHK
bool "ST 8815 Nomadik Hardware Kit (evaluation board)"
select CLKSRC_NOMADIK_MTU
select NOMADIK_8815
select I2C
select I2C_ALGOBIT
endmenu
config NOMADIK_8815
bool
config I2C_BITBANG_8815NHK
tristate "Driver for bit-bang busses found on the 8815 NHK"
depends on I2C && MACH_NOMADIK_8815NHK
depends on PINCTRL_NOMADIK
default y
select I2C_ALGOBIT
endif
arch/arm/mach-nomadik/Makefile
View file @ a8f3740f
......@@ -9,9 +9,3 @@
# Cpu revision
obj-$(CONFIG_NOMADIK_8815) += cpu-8815.o
# Specific board support
obj-$(CONFIG_MACH_NOMADIK_8815NHK) += board-nhk8815.o
# Nomadik extra devices
obj-$(CONFIG_I2C_BITBANG_8815NHK) += i2c-8815nhk.o
arch/arm/mach-nomadik/board-nhk8815.c deleted 100644 → 0
View file @ 6c5096e5
/*
* linux/arch/arm/mach-nomadik/board-8815nhk.c
*
* Copyright (C) STMicroelectronics
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2, as
* published by the Free Software Foundation.
*
* NHK15 board specifc driver definition
*/
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/amba/bus.h>
#include <linux/amba/mmci.h>
#include <linux/interrupt.h>
#include <linux/gpio.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/fsmc.h>
#include <linux/mtd/onenand.h>
#include <linux/mtd/partitions.h>
#include <linux/i2c.h>
#include <linux/io.h>
#include <linux/pinctrl/machine.h>
#include <linux/platform_data/pinctrl-nomadik.h>
#include <linux/platform_data/clocksource-nomadik-mtu.h>
#include <asm/sizes.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/flash.h>
#include <asm/mach/time.h>
#include <mach/irqs.h>
#include "cpu-8815.h"
/* Initial value for SRC control register: all timers use MXTAL/8 source */
#define SRC_CR_INIT_MASK 0x00007fff
#define SRC_CR_INIT_VAL 0x2aaa8000
#define ALE_OFF 0x1000000
#define CLE_OFF 0x800000
/* These addresses span 16MB, so use three individual pages */
static struct resource nhk8815_nand_resources[] = {
{
.name = "nand_data",
.start = 0x40000000,
.end = 0x40000000 + SZ_16K - 1,
.flags = IORESOURCE_MEM,
}, {
.name = "nand_addr",
.start = 0x40000000 + ALE_OFF,
.end = 0x40000000 +ALE_OFF + SZ_16K - 1,
.flags = IORESOURCE_MEM,
}, {
.name = "nand_cmd",
.start = 0x40000000 + CLE_OFF,
.end = 0x40000000 + CLE_OFF + SZ_16K - 1,
.flags = IORESOURCE_MEM,
}, {
.name = "fsmc_regs",
.start = NOMADIK_FSMC_BASE,
.end = NOMADIK_FSMC_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
};
/*
* These partitions are the same as those used in the 2.6.20 release
* shipped by the vendor; the first two partitions are mandated
* by the boot ROM, and the bootloader area is somehow oversized...
*/
static struct mtd_partition nhk8815_partitions[] = {
{
.name = "X-Loader(NAND)",
.offset = 0,
.size = SZ_256K,
}, {
.name = "MemInit(NAND)",
.offset = MTDPART_OFS_APPEND,
.size = SZ_256K,
}, {
.name = "BootLoader(NAND)",
.offset = MTDPART_OFS_APPEND,
.size = SZ_2M,
}, {
.name = "Kernel zImage(NAND)",
.offset = MTDPART_OFS_APPEND,
.size = 3 * SZ_1M,
}, {
.name = "Root Filesystem(NAND)",
.offset = MTDPART_OFS_APPEND,
.size = 22 * SZ_1M,
}, {
.name = "User Filesystem(NAND)",
.offset = MTDPART_OFS_APPEND,
.size = MTDPART_SIZ_FULL,
}
};
static struct fsmc_nand_timings nhk8815_nand_timings = {
.thiz = 0,
.thold = 0x10,
.twait = 0x0A,
.tset = 0,
};
static struct fsmc_nand_platform_data nhk8815_nand_platform_data = {
.nand_timings = &nhk8815_nand_timings,
.partitions = nhk8815_partitions,
.nr_partitions = ARRAY_SIZE(nhk8815_partitions),
.width = FSMC_NAND_BW8,
};
static struct platform_device nhk8815_nand_device = {
.name = "fsmc-nand",
.id = -1,
.resource = nhk8815_nand_resources,
.num_resources = ARRAY_SIZE(nhk8815_nand_resources),
.dev = {
.platform_data = &nhk8815_nand_platform_data,
},
};
/* These are the partitions for the OneNand device, different from above */
static struct mtd_partition nhk8815_onenand_partitions[] = {
{
.name = "X-Loader(OneNAND)",
.offset = 0,
.size = SZ_256K,
}, {
.name = "MemInit(OneNAND)",
.offset = MTDPART_OFS_APPEND,
.size = SZ_256K,
}, {
.name = "BootLoader(OneNAND)",
.offset = MTDPART_OFS_APPEND,
.size = SZ_2M-SZ_256K,
}, {
.name = "SysImage(OneNAND)",
.offset = MTDPART_OFS_APPEND,
.size = 4 * SZ_1M,
}, {
.name = "Root Filesystem(OneNAND)",
.offset = MTDPART_OFS_APPEND,
.size = 22 * SZ_1M,
}, {
.name = "User Filesystem(OneNAND)",
.offset = MTDPART_OFS_APPEND,
.size = MTDPART_SIZ_FULL,
}
};
static struct onenand_platform_data nhk8815_onenand_data = {
.parts = nhk8815_onenand_partitions,
.nr_parts = ARRAY_SIZE(nhk8815_onenand_partitions),
};
static struct resource nhk8815_onenand_resource[] = {
{
.start = 0x30000000,
.end = 0x30000000 + SZ_128K - 1,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device nhk8815_onenand_device = {
.name = "onenand-flash",
.id = -1,
.dev = {
.platform_data = &nhk8815_onenand_data,
},
.resource = nhk8815_onenand_resource,
.num_resources = ARRAY_SIZE(nhk8815_onenand_resource),
};
/* bus control reg. and bus timing reg. for CS0..CS3 */
#define FSMC_BCR(x) (NOMADIK_FSMC_VA + (x << 3))
#define FSMC_BTR(x) (NOMADIK_FSMC_VA + (x << 3) + 0x04)
static void __init nhk8815_onenand_init(void)
{
#ifdef CONFIG_MTD_ONENAND
/* Set up SMCS0 for OneNand */
writel(0x000030db, FSMC_BCR(0));
writel(0x02100551, FSMC_BTR(0));
#endif
}
static struct mmci_platform_data mmcsd_plat_data = {
.ocr_mask = MMC_VDD_29_30,
.f_max = 48000000,
.gpio_wp = -1,
.gpio_cd = 111,
.cd_invert = true,
.capabilities = MMC_CAP_MMC_HIGHSPEED |
MMC_CAP_SD_HIGHSPEED | MMC_CAP_4_BIT_DATA,
};
static int __init nhk8815_mmcsd_init(void)
{
int ret;
ret = gpio_request(112, "card detect bias");
if (ret)
return ret;
gpio_direction_output(112, 0);
amba_apb_device_add(NULL, "mmci", NOMADIK_SDI_BASE, SZ_4K, IRQ_SDMMC, 0, &mmcsd_plat_data, 0x10180180);
return 0;
}
module_init(nhk8815_mmcsd_init);
static struct resource nhk8815_eth_resources[] = {
{
.name = "smc91x-regs",
.start = 0x34000000 + 0x300,
.end = 0x34000000 + SZ_64K - 1,
.flags = IORESOURCE_MEM,
}, {
.start = NOMADIK_GPIO_TO_IRQ(115),
.end = NOMADIK_GPIO_TO_IRQ(115),
.flags = IORESOURCE_IRQ | IRQF_TRIGGER_RISING,
}
};
static struct platform_device nhk8815_eth_device = {
.name = "smc91x",
.resource = nhk8815_eth_resources,
.num_resources = ARRAY_SIZE(nhk8815_eth_resources),
};
static int __init nhk8815_eth_init(void)
{
int gpio_nr = 115; /* hardwired in the board */
int err;
err = gpio_request(gpio_nr, "eth_irq");
if (!err) err = nmk_gpio_set_mode(gpio_nr, NMK_GPIO_ALT_GPIO);
if (!err) err = gpio_direction_input(gpio_nr);
if (err)
pr_err("Error %i in %s\n", err, __func__);
return err;
}
device_initcall(nhk8815_eth_init);
static struct platform_device *nhk8815_platform_devices[] __initdata = {
&nhk8815_nand_device,
&nhk8815_onenand_device,
&nhk8815_eth_device,
/* will add more devices */
};
static void __init nomadik_timer_init(void)
{
u32 src_cr;
/* Configure timer sources in "system reset controller" ctrl reg */
src_cr = readl(io_p2v(NOMADIK_SRC_BASE));
src_cr &= SRC_CR_INIT_MASK;
src_cr |= SRC_CR_INIT_VAL;
writel(src_cr, io_p2v(NOMADIK_SRC_BASE));
nmdk_timer_init(io_p2v(NOMADIK_MTU0_BASE), IRQ_MTU0);
}
static struct i2c_board_info __initdata nhk8815_i2c0_devices[] = {
{
I2C_BOARD_INFO("stw4811", 0x2d),
},
};
static struct i2c_board_info __initdata nhk8815_i2c1_devices[] = {
{
I2C_BOARD_INFO("camera", 0x10),
},
{
I2C_BOARD_INFO("stw5095", 0x1a),
},
{
I2C_BOARD_INFO("lis3lv02dl", 0x1d),
},
};
static struct i2c_board_info __initdata nhk8815_i2c2_devices[] = {
{
I2C_BOARD_INFO("stw4811-usb", 0x2d),
},
};
static unsigned long out_low[] = { PIN_OUTPUT_LOW };
static unsigned long out_high[] = { PIN_OUTPUT_HIGH };
static unsigned long in_nopull[] = { PIN_INPUT_NOPULL };
static unsigned long in_pullup[] = { PIN_INPUT_PULLUP };
static struct pinctrl_map __initdata nhk8815_pinmap[] = {
PIN_MAP_MUX_GROUP_DEFAULT("uart0", "pinctrl-stn8815", "u0_a_1", "u0"),
PIN_MAP_MUX_GROUP_DEFAULT("uart1", "pinctrl-stn8815", "u1_a_1", "u1"),
/* Hog in MMC/SD card mux */
PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-stn8815", "mmcsd_a_1", "mmcsd"),
/* MCCLK */
PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO8_B10", out_low),
/* MCCMD */
PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO9_A10", in_pullup),
/* MCCMDDIR */
PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO10_C11", out_high),
/* MCDAT3-0 */
PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO11_B11", in_pullup),
PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO12_A11", in_pullup),
PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO13_C12", in_pullup),
PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO14_B12", in_pullup),
/* MCDAT0DIR */
PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO15_A12", out_high),
/* MCDAT31DIR */
PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO16_C13", out_high),
/* MCMSFBCLK */
PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO24_C15", in_pullup),
/* CD input GPIO */
PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO111_H21", in_nopull),
/* CD bias drive */
PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO112_J21", out_low),
};
static void __init nhk8815_platform_init(void)
{
pinctrl_register_mappings(nhk8815_pinmap, ARRAY_SIZE(nhk8815_pinmap));
cpu8815_platform_init();
nhk8815_onenand_init();
platform_add_devices(nhk8815_platform_devices,
ARRAY_SIZE(nhk8815_platform_devices));
amba_apb_device_add(NULL, "uart0", NOMADIK_UART0_BASE, SZ_4K, IRQ_UART0, 0, NULL, 0);
amba_apb_device_add(NULL, "uart1", NOMADIK_UART1_BASE, SZ_4K, IRQ_UART1, 0, NULL, 0);
i2c_register_board_info(0, nhk8815_i2c0_devices,
ARRAY_SIZE(nhk8815_i2c0_devices));
i2c_register_board_info(1, nhk8815_i2c1_devices,
ARRAY_SIZE(nhk8815_i2c1_devices));
i2c_register_board_info(2, nhk8815_i2c2_devices,
ARRAY_SIZE(nhk8815_i2c2_devices));
}
MACHINE_START(NOMADIK, "NHK8815")
/* Maintainer: ST MicroElectronics */
.atag_offset = 0x100,
.map_io = cpu8815_map_io,
.init_irq = cpu8815_init_irq,
.init_time = nomadik_timer_init,
.init_machine = nhk8815_platform_init,
.restart = cpu8815_restart,
MACHINE_END
arch/arm/mach-nomadik/cpu-8815.c
View file @ a8f3740f
This diff is collapsed.
arch/arm/mach-nomadik/cpu-8815.h deleted 100644 → 0
View file @ 6c5096e5
extern void cpu8815_map_io(void);
extern void cpu8815_platform_init(void);
extern void cpu8815_init_irq(void);
extern void cpu8815_restart(char, const char *);
arch/arm/mach-nomadik/i2c-8815nhk.c deleted 100644 → 0
View file @ 6c5096e5
#include <linux/module.h>
#include <linux/init.h>
#include <linux/i2c.h>
#include <linux/i2c-algo-bit.h>
#include <linux/i2c-gpio.h>
#include <linux/platform_device.h>
#include <linux/platform_data/pinctrl-nomadik.h>
/*
* There are two busses in the 8815NHK.
* They could, in theory, be driven by the hardware component, but we
* use bit-bang through GPIO by now, to keep things simple
*/
/* I2C0 connected to the STw4811 power management chip */
static struct i2c_gpio_platform_data nhk8815_i2c_data0 = {
/* keep defaults for timeouts; pins are push-pull bidirectional */
.scl_pin = 62,
.sda_pin = 63,
};
/* I2C1 connected to various sensors */
static struct i2c_gpio_platform_data nhk8815_i2c_data1 = {
/* keep defaults for timeouts; pins are push-pull bidirectional */
.scl_pin = 53,
.sda_pin = 54,
};
/* I2C2 connected to the USB portions of the STw4811 only */
static struct i2c_gpio_platform_data nhk8815_i2c_data2 = {
/* keep defaults for timeouts; pins are push-pull bidirectional */
.scl_pin = 73,
.sda_pin = 74,
};
static struct platform_device nhk8815_i2c_dev0 = {
.name = "i2c-gpio",
.id = 0,
.dev = {
.platform_data = &nhk8815_i2c_data0,
},
};
static struct platform_device nhk8815_i2c_dev1 = {
.name = "i2c-gpio",
.id = 1,
.dev = {
.platform_data = &nhk8815_i2c_data1,
},
};
static struct platform_device nhk8815_i2c_dev2 = {
.name = "i2c-gpio",
.id = 2,
.dev = {
.platform_data = &nhk8815_i2c_data2,
},
};
static pin_cfg_t cpu8815_pins_i2c[] = {
PIN_CFG_INPUT(62, GPIO, PULLUP),
PIN_CFG_INPUT(63, GPIO, PULLUP),
PIN_CFG_INPUT(53, GPIO, PULLUP),
PIN_CFG_INPUT(54, GPIO, PULLUP),
PIN_CFG_INPUT(73, GPIO, PULLUP),
PIN_CFG_INPUT(74, GPIO, PULLUP),
};
static int __init nhk8815_i2c_init(void)
{
nmk_config_pins(cpu8815_pins_i2c, ARRAY_SIZE(cpu8815_pins_i2c));
platform_device_register(&nhk8815_i2c_dev0);
platform_device_register(&nhk8815_i2c_dev1);
platform_device_register(&nhk8815_i2c_dev2);
return 0;
}
static void __exit nhk8815_i2c_exit(void)
{
platform_device_unregister(&nhk8815_i2c_dev0);
platform_device_unregister(&nhk8815_i2c_dev1);
platform_device_unregister(&nhk8815_i2c_dev2);
return;
}
module_init(nhk8815_i2c_init);
module_exit(nhk8815_i2c_exit);
arch/arm/mach-nomadik/include/mach/hardware.h deleted 100644 → 0
View file @ 6c5096e5
/*
* This file contains the hardware definitions of the Nomadik.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* YOU should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_ARCH_HARDWARE_H
#define __ASM_ARCH_HARDWARE_H
/* Nomadik registers live from 0x1000.0000 to 0x1023.0000 -- currently */
#define NOMADIK_IO_VIRTUAL 0xF0000000 /* VA of IO */
#define NOMADIK_IO_PHYSICAL 0x10000000 /* PA of IO */
#define NOMADIK_IO_SIZE 0x00300000 /* 3MB for all regs */
/* used in C code, so cast to proper type */
#define io_p2v(x) ((void __iomem *)(x) \
- NOMADIK_IO_PHYSICAL + NOMADIK_IO_VIRTUAL)
#define io_v2p(x) ((unsigned long)(x) \
- NOMADIK_IO_VIRTUAL + NOMADIK_IO_PHYSICAL)
/* used in asm code, so no casts */
#define IO_ADDRESS(x) IOMEM((x) - NOMADIK_IO_PHYSICAL + NOMADIK_IO_VIRTUAL)
/*
* Base address defination for Nomadik Onchip Logic Block
*/
#define NOMADIK_FSMC_BASE 0x10100000 /* FSMC registers */
#define NOMADIK_SDRAMC_BASE 0x10110000 /* SDRAM Controller */
#define NOMADIK_CLCDC_BASE 0x10120000 /* CLCD Controller */
#define NOMADIK_MDIF_BASE 0x10120000 /* MDIF */
#define NOMADIK_DMA0_BASE 0x10130000 /* DMA0 Controller */
#define NOMADIK_IC_BASE 0x10140000 /* Vectored Irq Controller */
#define NOMADIK_DMA1_BASE 0x10150000 /* DMA1 Controller */
#define NOMADIK_USB_BASE 0x10170000 /* USB-OTG conf reg base */
#define NOMADIK_CRYP_BASE 0x10180000 /* Crypto processor */
#define NOMADIK_SHA1_BASE 0x10190000 /* SHA-1 Processor */
#define NOMADIK_XTI_BASE 0x101A0000 /* XTI */
#define NOMADIK_RNG_BASE 0x101B0000 /* Random number generator */
#define NOMADIK_SRC_BASE 0x101E0000 /* SRC base */
#define NOMADIK_WDOG_BASE 0x101E1000 /* Watchdog */
#define NOMADIK_MTU0_BASE 0x101E2000 /* Multiple Timer 0 */
#define NOMADIK_MTU1_BASE 0x101E3000 /* Multiple Timer 1 */
#define NOMADIK_GPIO0_BASE 0x101E4000 /* GPIO0 */
#define NOMADIK_GPIO1_BASE 0x101E5000 /* GPIO1 */
#define NOMADIK_GPIO2_BASE 0x101E6000 /* GPIO2 */
#define NOMADIK_GPIO3_BASE 0x101E7000 /* GPIO3 */
#define NOMADIK_RTC_BASE 0x101E8000 /* Real Time Clock base */
#define NOMADIK_PMU_BASE 0x101E9000 /* Power Management Unit */
#define NOMADIK_OWM_BASE 0x101EA000 /* One wire master */
#define NOMADIK_SCR_BASE 0x101EF000 /* Secure Control registers */
#define NOMADIK_MSP2_BASE 0x101F0000 /* MSP 2 interface */
#define NOMADIK_MSP1_BASE 0x101F1000 /* MSP 1 interface */
#define NOMADIK_UART2_BASE 0x101F2000 /* UART 2 interface */
#define NOMADIK_SSIRx_BASE 0x101F3000 /* SSI 8-ch rx interface */
#define NOMADIK_SSITx_BASE 0x101F4000 /* SSI 8-ch tx interface */
#define NOMADIK_MSHC_BASE 0x101F5000 /* Memory Stick(Pro) Host */
#define NOMADIK_SDI_BASE 0x101F6000 /* SD-card/MM-Card */
#define NOMADIK_I2C1_BASE 0x101F7000 /* I2C1 interface */
#define NOMADIK_I2C0_BASE 0x101F8000 /* I2C0 interface */
#define NOMADIK_MSP0_BASE 0x101F9000 /* MSP 0 interface */
#define NOMADIK_FIRDA_BASE 0x101FA000 /* FIrDA interface */
#define NOMADIK_UART1_BASE 0x101FB000 /* UART 1 interface */
#define NOMADIK_SSP_BASE 0x101FC000 /* SSP interface */
#define NOMADIK_UART0_BASE 0x101FD000 /* UART 0 interface */
#define NOMADIK_SGA_BASE 0x101FE000 /* SGA interface */
#define NOMADIK_L2CC_BASE 0x10210000 /* L2 Cache controller */
/* Other ranges, not for p2v/v2p */
#define NOMADIK_BACKUP_RAM 0x80010000
#define NOMADIK_EBROM 0x80000000 /* Embedded boot ROM */
#define NOMADIK_HAMACV_DMEM_BASE 0xA0100000 /* HAMACV Data Memory Start */
#define NOMADIK_HAMACV_DMEM_END 0xA01FFFFF /* HAMACV Data Memory End */
#define NOMADIK_HAMACA_DMEM 0xA0200000 /* HAMACA Data Memory Space */
#define NOMADIK_FSMC_VA IO_ADDRESS(NOMADIK_FSMC_BASE)
#define NOMADIK_MTU0_VA IO_ADDRESS(NOMADIK_MTU0_BASE)
#define NOMADIK_MTU1_VA IO_ADDRESS(NOMADIK_MTU1_BASE)
#endif /* __ASM_ARCH_HARDWARE_H */
arch/arm/mach-nomadik/include/mach/irqs.h
View file @ a8f3740f
......@@ -20,8 +20,6 @@
#ifndef __ASM_ARCH_IRQS_H
#define __ASM_ARCH_IRQS_H
#include <mach/hardware.h>
#define IRQ_VIC_START 32 /* first VIC interrupt is 1 */
/*
......
arch/arm/mach-nomadik/include/mach/uncompress.h
View file @ a8f3740f
......@@ -21,7 +21,6 @@
#include <asm/setup.h>
#include <asm/io.h>
#include <mach/hardware.h>
/* we need the constants in amba/serial.h, but it refers to amba_device */
struct amba_device;
......
drivers/clk/tegra/clk-super.c
View file @ a8f3740f
......@@ -73,7 +73,12 @@ static int clk_super_set_parent(struct clk_hw *hw, u8 index)
{
struct tegra_clk_super_mux *mux = to_clk_super_mux(hw);
u32 val, state;
int err = 0;
u8 parent_index, shift;
unsigned long flags = 0;
if (mux->lock)
spin_lock_irqsave(mux->lock, flags);
val = readl_relaxed(mux->reg);
state = val & SUPER_STATE_MASK;
......@@ -92,8 +97,10 @@ static int clk_super_set_parent(struct clk_hw *hw, u8 index)
(index == mux->pllx_index))) {
parent_index = clk_super_get_parent(hw);
if ((parent_index == mux->div2_index) ||
(parent_index == mux->pllx_index))
return -EINVAL;
(parent_index == mux->pllx_index)) {
err = -EINVAL;
goto out;
}
val ^= SUPER_LP_DIV2_BYPASS;
writel_relaxed(val, mux->reg);
......@@ -107,7 +114,12 @@ static int clk_super_set_parent(struct clk_hw *hw, u8 index)
writel_relaxed(val, mux->reg);
udelay(2);
return 0;
out:
if (mux->lock)
spin_unlock_irqrestore(mux->lock, flags);
return err;
}
const struct clk_ops tegra_clk_super_ops = {
......
drivers/clk/tegra/clk-tegra20.c
View file @ a8f3740f
......@@ -194,6 +194,7 @@ static void __iomem *clk_base;
static void __iomem *pmc_base;
static DEFINE_SPINLOCK(pll_div_lock);
static DEFINE_SPINLOCK(sysrate_lock);
#define TEGRA_INIT_DATA_MUX(_name, _con_id, _dev_id, _parents, _offset, \
_clk_num, _regs, _gate_flags, _clk_id) \
......@@ -239,8 +240,8 @@ enum tegra20_clk {
uartb = 96, vfir, spdif_in, spdif_out, vi, vi_sensor, tvo, cve,
osc, clk_32k, clk_m, sclk, cclk, hclk, pclk, blink, pll_a, pll_a_out0,
pll_c, pll_c_out1, pll_d, pll_d_out0, pll_e, pll_m, pll_m_out1,
pll_p, pll_p_out1, pll_p_out2, pll_p_out3, pll_p_out4, pll_u,
pll_x, audio, pll_ref, twd, clk_max,
pll_p, pll_p_out1, pll_p_out2, pll_p_out3, pll_p_out4, pll_s, pll_u,
pll_x, cop, audio, pll_ref, twd, clk_max,
};
static struct clk *clks[clk_max];
......@@ -768,19 +769,21 @@ static void tegra20_super_clk_init(void)
/* HCLK */
clk = clk_register_divider(NULL, "hclk_div", "sclk", 0,
clk_base + CLK_SYSTEM_RATE, 4, 2, 0, NULL);
clk_base + CLK_SYSTEM_RATE, 4, 2, 0,
&sysrate_lock);
clk = clk_register_gate(NULL, "hclk", "hclk_div", CLK_SET_RATE_PARENT,
clk_base + CLK_SYSTEM_RATE, 7,
CLK_GATE_SET_TO_DISABLE, NULL);
CLK_GATE_SET_TO_DISABLE, &sysrate_lock);
clk_register_clkdev(clk, "hclk", NULL);
clks[hclk] = clk;
/* PCLK */
clk = clk_register_divider(NULL, "pclk_div", "hclk", 0,
clk_base + CLK_SYSTEM_RATE, 0, 2, 0, NULL);
clk_base + CLK_SYSTEM_RATE, 0, 2, 0,
&sysrate_lock);
clk = clk_register_gate(NULL, "pclk", "pclk_div", CLK_SET_RATE_PARENT,
clk_base + CLK_SYSTEM_RATE, 3,
CLK_GATE_SET_TO_DISABLE, NULL);
CLK_GATE_SET_TO_DISABLE, &sysrate_lock);
clk_register_clkdev(clk, "pclk", NULL);
clks[pclk] = clk;
......@@ -1251,8 +1254,11 @@ static __initdata struct tegra_clk_init_table init_table[] = {
{csite, clk_max, 0, 1},
{emc, clk_max, 0, 1},
{cclk, clk_max, 0, 1},
{uarta, pll_p, 0, 1},
{uartd, pll_p, 0, 1},
{uarta, pll_p, 0, 0},
{uartb, pll_p, 0, 0},
{uartc, pll_p, 0, 0},
{uartd, pll_p, 0, 0},
{uarte, pll_p, 0, 0},
{usbd, clk_max, 12000000, 0},
{usb2, clk_max, 12000000, 0},
{usb3, clk_max, 12000000, 0},
......
drivers/clk/tegra/clk-tegra30.c
View file @ a8f3740f
......@@ -275,6 +275,7 @@ static DEFINE_SPINLOCK(clk_out_lock);
static DEFINE_SPINLOCK(pll_div_lock);
static DEFINE_SPINLOCK(cml_lock);
static DEFINE_SPINLOCK(pll_d_lock);
static DEFINE_SPINLOCK(sysrate_lock);
#define TEGRA_INIT_DATA_MUX(_name, _con_id, _dev_id, _parents, _offset, \
_clk_num, _regs, _gate_flags, _clk_id) \
......@@ -327,21 +328,21 @@ enum tegra30_clk {
kbc = 36, statmon, pmc, kfuse = 40, sbc1, nor, sbc2 = 44, sbc3 = 46,
i2c5, dsia, mipi = 50, hdmi, csi, tvdac, i2c2, uartc, emc = 57, usb2,
usb3, mpe, vde, bsea, bsev, speedo, uartd, uarte, i2c3, sbc4, sdmmc3,
pcie, owr, afi, csite, pciex, avpucq, la, dtv = 79, ndspeed, i2c_slow,
pcie, owr, afi, csite, pciex, avpucq, la, dtv = 79, ndspeed, i2cslow,
dsib, irama = 84, iramb, iramc, iramd, cram2, audio_2x = 90, csus = 92,
cdev1, cdev2, cpu_g = 96, cpu_lp, gr3d2, mselect, tsensor, i2s3, i2s4,
i2c4, sbc5, sbc6, d_audio, apbif, dam0, dam1, dam2, hda2codec_2x,
atomics, audio0_2x, audio1_2x, audio2_2x, audio3_2x, audio4_2x,
spdif_2x, actmon, extern1, extern2, extern3, sata_oob, sata, hda, se,
hda2hdmi, sata_cold, uartb = 160, vfir, spdif_out, spdif_in, vi,
vi_sensor, fuse, fuse_burn, cve, tvo, clk_32k, clk_m, clk_m_div2,
spdif_2x, actmon, extern1, extern2, extern3, sata_oob, sata, hda,
se = 127, hda2hdmi, sata_cold, uartb = 160, vfir, spdif_in, spdif_out,
vi, vi_sensor, fuse, fuse_burn, cve, tvo, clk_32k, clk_m, clk_m_div2,
clk_m_div4, pll_ref, pll_c, pll_c_out1, pll_m, pll_m_out1, pll_p,
pll_p_out1, pll_p_out2, pll_p_out3, pll_p_out4, pll_a, pll_a_out0,
pll_d, pll_d_out0, pll_d2, pll_d2_out0, pll_u, pll_x, pll_x_out0, pll_e,
spdif_in_sync, i2s0_sync, i2s1_sync, i2s2_sync, i2s3_sync, i2s4_sync,
vimclk_sync, audio0, audio1, audio2, audio3, audio4, spdif, clk_out_1,
clk_out_2, clk_out_3, sclk, blink, cclk_g, cclk_lp, twd, cml0, cml1,
i2cslow, hclk, pclk, clk_out_1_mux = 300, clk_max
hclk, pclk, clk_out_1_mux = 300, clk_max
};
static struct clk *clks[clk_max];
......@@ -1249,16 +1250,16 @@ static void __init tegra30_pmc_clk_init(void)
}
const char *cclk_g_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
"pll_p_cclkg", "pll_p_out4_cclkg",
"pll_p_out3_cclkg", "unused", "pll_x" };
const char *cclk_lp_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
"pll_p_cclklp", "pll_p_out4_cclklp",
"pll_p_out3_cclklp", "unused", "pll_x",
"pll_x_out0" };
const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4",
"pll_p_out3", "pll_p_out2", "unused",
"clk_32k", "pll_m_out1" };
static const char *cclk_g_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
"pll_p_cclkg", "pll_p_out4_cclkg",
"pll_p_out3_cclkg", "unused", "pll_x" };
static const char *cclk_lp_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
"pll_p_cclklp", "pll_p_out4_cclklp",
"pll_p_out3_cclklp", "unused", "pll_x",
"pll_x_out0" };
static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4",
"pll_p_out3", "pll_p_out2", "unused",
"clk_32k", "pll_m_out1" };
static void __init tegra30_super_clk_init(void)
{
......@@ -1348,19 +1349,21 @@ static void __init tegra30_super_clk_init(void)
/* HCLK */
clk = clk_register_divider(NULL, "hclk_div", "sclk", 0,
clk_base + SYSTEM_CLK_RATE, 4, 2, 0, NULL);
clk_base + SYSTEM_CLK_RATE, 4, 2, 0,
&sysrate_lock);
clk = clk_register_gate(NULL, "hclk", "hclk_div", CLK_SET_RATE_PARENT,
clk_base + SYSTEM_CLK_RATE, 7,
CLK_GATE_SET_TO_DISABLE, NULL);
CLK_GATE_SET_TO_DISABLE, &sysrate_lock);
clk_register_clkdev(clk, "hclk", NULL);
clks[hclk] = clk;
/* PCLK */
clk = clk_register_divider(NULL, "pclk_div", "hclk", 0,
clk_base + SYSTEM_CLK_RATE, 0, 2, 0, NULL);
clk_base + SYSTEM_CLK_RATE, 0, 2, 0,
&sysrate_lock);
clk = clk_register_gate(NULL, "pclk", "pclk_div", CLK_SET_RATE_PARENT,
clk_base + SYSTEM_CLK_RATE, 3,
CLK_GATE_SET_TO_DISABLE, NULL);
CLK_GATE_SET_TO_DISABLE, &sysrate_lock);
clk_register_clkdev(clk, "pclk", NULL);
clks[pclk] = clk;
......@@ -1874,7 +1877,11 @@ static struct tegra_cpu_car_ops tegra30_cpu_car_ops = {
};
static __initdata struct tegra_clk_init_table init_table[] = {
{uarta, pll_p, 408000000, 1},
{uarta, pll_p, 408000000, 0},
{uartb, pll_p, 408000000, 0},
{uartc, pll_p, 408000000, 0},
{uartd, pll_p, 408000000, 0},
{uarte, pll_p, 408000000, 0},
{pll_a, clk_max, 564480000, 1},
{pll_a_out0, clk_max, 11289600, 1},
{extern1, pll_a_out0, 0, 1},
......
drivers/mtd/nand/fsmc_nand.c
View file @ a8f3740f
......@@ -1211,6 +1211,7 @@ static SIMPLE_DEV_PM_OPS(fsmc_nand_pm_ops, fsmc_nand_suspend, fsmc_nand_resume);
#ifdef CONFIG_OF
static const struct of_device_id fsmc_nand_id_table[] = {
{ .compatible = "st,spear600-fsmc-nand" },
{ .compatible = "stericsson,fsmc-nand" },
{}
};
MODULE_DEVICE_TABLE(of, fsmc_nand_id_table);
......
drivers/pinctrl/pinctrl-nomadik.c
View file @ a8f3740f
......@@ -2103,6 +2103,10 @@ static struct pinctrl_desc nmk_pinctrl_desc = {
};
static const struct of_device_id nmk_pinctrl_match[] = {
{
.compatible = "stericsson,nmk-pinctrl-stn8815",
.data = (void *)PINCTRL_NMK_STN8815,
},
{
.compatible = "stericsson,nmk-pinctrl",
.data = (void *)PINCTRL_NMK_DB8500,
......
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