Commit a9380b0f authored by Iyappan Subramanian's avatar Iyappan Subramanian Committed by David S. Miller

drivers: net: xgene: Add support for Jumbo frame

This patch adds support for jumbo frame, by allocating
additional buffer (page) pool and configuring the hardware.
Signed-off-by: default avatarIyappan Subramanian <isubramanian@apm.com>
Signed-off-by: default avatarQuan Nguyen <qnguyen@apm.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent d6d48969
...@@ -679,6 +679,9 @@ static void xgene_gport_shutdown(struct xgene_enet_pdata *pdata) ...@@ -679,6 +679,9 @@ static void xgene_gport_shutdown(struct xgene_enet_pdata *pdata)
for (i = 0; i < pdata->rxq_cnt; i++) { for (i = 0; i < pdata->rxq_cnt; i++) {
ring = pdata->rx_ring[i]->buf_pool; ring = pdata->rx_ring[i]->buf_pool;
pb |= BIT(xgene_enet_get_fpsel(ring->id)); pb |= BIT(xgene_enet_get_fpsel(ring->id));
ring = pdata->rx_ring[i]->page_pool;
if (ring)
pb |= BIT(xgene_enet_get_fpsel(ring->id));
} }
xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIFPRESET_ADDR, pb); xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIFPRESET_ADDR, pb);
......
...@@ -41,11 +41,14 @@ ...@@ -41,11 +41,14 @@
#include "../../../phy/mdio-xgene.h" #include "../../../phy/mdio-xgene.h"
#define XGENE_DRV_VERSION "v1.0" #define XGENE_DRV_VERSION "v1.0"
#define XGENE_ENET_MAX_MTU 1536 #define XGENE_ENET_STD_MTU 1536
#define SKB_BUFFER_SIZE (XGENE_ENET_MAX_MTU - NET_IP_ALIGN) #define XGENE_ENET_MAX_MTU 9600
#define SKB_BUFFER_SIZE (XGENE_ENET_STD_MTU - NET_IP_ALIGN)
#define BUFLEN_16K (16 * 1024) #define BUFLEN_16K (16 * 1024)
#define NUM_PKT_BUF 64 #define NUM_PKT_BUF 1024
#define NUM_BUFPOOL 32 #define NUM_BUFPOOL 32
#define NUM_NXTBUFPOOL 8
#define MAX_EXP_BUFFS 256 #define MAX_EXP_BUFFS 256
#define NUM_MSS_REG 4 #define NUM_MSS_REG 4
#define XGENE_MIN_ENET_FRAME_SIZE 60 #define XGENE_MIN_ENET_FRAME_SIZE 60
...@@ -88,6 +91,12 @@ enum xgene_enet_id { ...@@ -88,6 +91,12 @@ enum xgene_enet_id {
XGENE_ENET2 XGENE_ENET2
}; };
enum xgene_enet_buf_len {
SIZE_2K = 2048,
SIZE_4K = 4096,
SIZE_16K = 16384
};
/* software context of a descriptor ring */ /* software context of a descriptor ring */
struct xgene_enet_desc_ring { struct xgene_enet_desc_ring {
struct net_device *ndev; struct net_device *ndev;
...@@ -107,11 +116,14 @@ struct xgene_enet_desc_ring { ...@@ -107,11 +116,14 @@ struct xgene_enet_desc_ring {
dma_addr_t irq_mbox_dma; dma_addr_t irq_mbox_dma;
void *irq_mbox_addr; void *irq_mbox_addr;
u16 dst_ring_num; u16 dst_ring_num;
u8 nbufpool; u16 nbufpool;
int npagepool;
u8 index; u8 index;
u32 flags;
struct sk_buff *(*rx_skb); struct sk_buff *(*rx_skb);
struct sk_buff *(*cp_skb); struct sk_buff *(*cp_skb);
dma_addr_t *frag_dma_addr; dma_addr_t *frag_dma_addr;
struct page *(*frag_page);
enum xgene_enet_ring_cfgsize cfgsize; enum xgene_enet_ring_cfgsize cfgsize;
struct xgene_enet_desc_ring *cp_ring; struct xgene_enet_desc_ring *cp_ring;
struct xgene_enet_desc_ring *buf_pool; struct xgene_enet_desc_ring *buf_pool;
......
...@@ -119,6 +119,7 @@ static void xgene_enet_set_ring_id(struct xgene_enet_desc_ring *ring) ...@@ -119,6 +119,7 @@ static void xgene_enet_set_ring_id(struct xgene_enet_desc_ring *ring)
ring_id_buf = (ring->num << 9) & GENMASK(18, 9); ring_id_buf = (ring->num << 9) & GENMASK(18, 9);
ring_id_buf |= PREFETCH_BUF_EN; ring_id_buf |= PREFETCH_BUF_EN;
if (is_bufpool) if (is_bufpool)
ring_id_buf |= IS_BUFFER_POOL; ring_id_buf |= IS_BUFFER_POOL;
......
...@@ -536,6 +536,9 @@ static void xgene_enet_shutdown(struct xgene_enet_pdata *p) ...@@ -536,6 +536,9 @@ static void xgene_enet_shutdown(struct xgene_enet_pdata *p)
for (i = 0; i < p->rxq_cnt; i++) { for (i = 0; i < p->rxq_cnt; i++) {
ring = p->rx_ring[i]->buf_pool; ring = p->rx_ring[i]->buf_pool;
pb |= BIT(xgene_enet_get_fpsel(ring->id)); pb |= BIT(xgene_enet_get_fpsel(ring->id));
ring = p->rx_ring[i]->page_pool;
if (ring)
pb |= BIT(xgene_enet_get_fpsel(ring->id));
} }
xgene_enet_wr_ring_if(p, ENET_CFGSSQMIFPRESET_ADDR, pb); xgene_enet_wr_ring_if(p, ENET_CFGSSQMIFPRESET_ADDR, pb);
......
...@@ -367,6 +367,7 @@ static void xgene_enet_xgcle_bypass(struct xgene_enet_pdata *pdata, ...@@ -367,6 +367,7 @@ static void xgene_enet_xgcle_bypass(struct xgene_enet_pdata *pdata,
CFG_CLE_FPSEL0_SET(&cb, fpsel); CFG_CLE_FPSEL0_SET(&cb, fpsel);
CFG_CLE_NXTFPSEL0_SET(&cb, nxtfpsel); CFG_CLE_NXTFPSEL0_SET(&cb, nxtfpsel);
xgene_enet_wr_csr(pdata, XCLE_BYPASS_REG1_ADDR, cb); xgene_enet_wr_csr(pdata, XCLE_BYPASS_REG1_ADDR, cb);
pr_info("+ cle_bypass: fpsel: %d nxtfpsel: %d\n", fpsel, nxtfpsel);
} }
static void xgene_enet_shutdown(struct xgene_enet_pdata *pdata) static void xgene_enet_shutdown(struct xgene_enet_pdata *pdata)
...@@ -380,6 +381,9 @@ static void xgene_enet_shutdown(struct xgene_enet_pdata *pdata) ...@@ -380,6 +381,9 @@ static void xgene_enet_shutdown(struct xgene_enet_pdata *pdata)
for (i = 0; i < pdata->rxq_cnt; i++) { for (i = 0; i < pdata->rxq_cnt; i++) {
ring = pdata->rx_ring[i]->buf_pool; ring = pdata->rx_ring[i]->buf_pool;
pb |= BIT(xgene_enet_get_fpsel(ring->id)); pb |= BIT(xgene_enet_get_fpsel(ring->id));
ring = pdata->rx_ring[i]->page_pool;
if (ring)
pb |= BIT(xgene_enet_get_fpsel(ring->id));
} }
xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIFPRESET_ADDR, pb); xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIFPRESET_ADDR, pb);
......
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