ppc: Freescale MPC52xx interrupt controller init code update

Part of the initialization code of the interrupt controller is
board-specific. It's mainly the external interrupt IRQ[0,3]
configuration. This moved in platform file by this ChangeSet.
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>

arch/ppc/platforms/lite5200.c

@@ -77,11 +77,42 @@ lite5200_show_cpuinfo(struct seq_file *m)
 	return 0;
 }
 
+static void __init
+lite5200_setup_cpu(void)
+{
+	struct mpc52xx_intr *intr;
+
+	u32 intr_ctrl;
+
+	/* Map zones */
+	intr = (struct mpc52xx_intr *)
+		ioremap(MPC52xx_INTR,sizeof(struct mpc52xx_intr));
+
+	if (!intr) {
+		printk("lite5200.c: Error while mapping INTR during lite5200_setup_cpu\n");
+		goto unmap_regs;
+	}
+
+	/* IRQ[0-3] setup : IRQ0     - Level Active Low  */
+	/*                  IRQ[1-3] - Level Active High */
+	intr_ctrl = in_be32(&intr->ctrl);
+	intr_ctrl &= ~0x00ff0000;
+	intr_ctrl |=  0x00c00000;
+	out_be32(&intr->ctrl, intr_ctrl);
+
+	/* Unmap reg zone */
+unmap_regs:
+	if (intr) iounmap(intr);
+}
+
 static void __init
 lite5200_setup_arch(void)
 {
 	/* Add board OCP definitions */
 	mpc52xx_add_board_devices(board_ocp);
+
+	/* CPU & Port mux setup */
+	lite5200_setup_cpu();
 }
 
 void __init

arch/ppc/syslib/mpc52xx_pic.c

@@ -180,6 +180,7 @@ void __init
 mpc52xx_init_irq(void)
 {
 	int i;
+	u32 intr_ctrl;
 
 	/* Remap the necessary zones */
 	intr = (struct mpc52xx_intr *)
@@ -195,12 +196,13 @@ mpc52xx_init_irq(void)
 	out_be32(&sdma->IntMask, 0xffffffff);	/* 1 means disabled */
 	out_be32(&intr->per_mask, 0x7ffffc00);	/* 1 means disabled */
 	out_be32(&intr->main_mask, 0x00010fff);	/* 1 means disabled */
-	out_be32(&intr->ctrl,
-			0x0f000000 |	/* clear IRQ 0-3 */
-			0x00c00000 |	/* IRQ0: level-sensitive, active low */
+	intr_ctrl = in_be32(&intr->ctrl);
+	intr_ctrl &=    0x00ff0000;	/* Keeps IRQ[0-3] config */
+	intr_ctrl |=	0x0f000000 |	/* clear IRQ 0-3 */
 			0x00001000 |	/* MEE master external enable */
 			0x00000000 |	/* 0 means disable IRQ 0-3 */
-			0x00000001);	/* CEb route critical normally */
+			0x00000001;	/* CEb route critical normally */
+	out_be32(&intr->ctrl, intr_ctrl);
 
 	/* Zero a bunch of the priority settings.  */
 	out_be32(&intr->per_pri1, 0);
@@ -214,6 +216,14 @@ mpc52xx_init_irq(void)
 		irq_desc[i].handler = &mpc52xx_ic;
 		irq_desc[i].status = IRQ_LEVEL;
 	}
+
+	#define IRQn_MODE(intr_ctrl,irq) (((intr_ctrl) >> (22-(i<<1))) & 0x03)
+	for (i=0 ; i<4 ; i++) {
+		int mode;
+		mode = IRQn_MODE(intr_ctrl,i);
+		if ((mode == 0x1) || (mode == 0x2))
+			irq_desc[i?MPC52xx_IRQ1+i-1:MPC52xx_IRQ0].status = 0;
+	}
 }
 
 int