Commit a9952a76 authored by Peter De Schrijver's avatar Peter De Schrijver

clk: tegra: Fix vic03 mux index

The vic03 mux uses a linear mapping.
Signed-off-by: default avatarPeter De Schrijver <pdeschrijver@nvidia.com>
parent 3de5bdfb
...@@ -371,9 +371,7 @@ static const char *mux_pllp3_pllc_clkm[] = { ...@@ -371,9 +371,7 @@ static const char *mux_pllp3_pllc_clkm[] = {
static const char *mux_pllm_pllc_pllp_plla_pllc2_c3_clkm[] = { static const char *mux_pllm_pllc_pllp_plla_pllc2_c3_clkm[] = {
"pll_m", "pll_c", "pll_p", "pll_a", "pll_c2", "pll_c3", "clk_m" "pll_m", "pll_c", "pll_p", "pll_a", "pll_c2", "pll_c3", "clk_m"
}; };
static u32 mux_pllm_pllc_pllp_plla_pllc2_c3_clkm_idx[] = { #define mux_pllm_pllc_pllp_plla_pllc2_c3_clkm_idx NULL
[0] = 0, [1] = 1, [2] = 2, [3] = 3, [4] = 4, [5] = 6,
};
static const char *mux_pllm_pllc2_c_c3_pllp_plla_pllc4[] = { static const char *mux_pllm_pllc2_c_c3_pllp_plla_pllc4[] = {
"pll_m", "pll_c2", "pll_c", "pll_c3", "pll_p", "pll_a_out0", "pll_c4", "pll_m", "pll_c2", "pll_c", "pll_c3", "pll_p", "pll_a_out0", "pll_c4",
......
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