Staging: benet: fix problems reported by checkpatch

Signed-off-by: Sathya Perla <sathyap@serverengines.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>

drivers/staging/benet/TODO

 TODO:
-	- fix minor checkpatch.pl issues
 	- remove wrappers around common iowrite functions
 	- full netdev audit of common problems/issues
 

drivers/staging/benet/asyncmesg.h

@@ -62,22 +62,6 @@ struct ASYNC_EVENT_TRAILER_AMAP {
  * port. The ARM firmware does not attempt to 'fail back' traffic to
  * the restored port.
  */
-#if 0
-struct BE_ASYNC_EVENT_LINK_STATE_AMAP {
-	struct BE_UEXACT8_AMAP port0_link_status;
-	struct BE_UEXACT8_AMAP port1_link_status;
-	struct BE_UEXACT8_AMAP active_port;
-	u8 rsvd0[8];	/* DWORD 0 */
-	struct BE_UEXACT8_AMAP port0_duplex;
-	struct BE_UEXACT8_AMAP port0_speed;
-	struct BE_UEXACT8_AMAP port1_duplex;
-	struct BE_UEXACT8_AMAP port1_speed;
-	struct BE_UEXACT8_AMAP port0_fault;
-	struct BE_UEXACT8_AMAP port1_fault;
-	u8 rsvd1[2][8];	/* DWORD 2 */
-	struct BE_ASYNC_EVENT_TRAILER_AMAP trailer;
-} __packed;
-#endif
 struct BE_ASYNC_EVENT_LINK_STATE_AMAP {
 	u8 port0_link_status[8];
 	u8 port1_link_status[8];

drivers/staging/benet/be_init.c

@@ -1083,7 +1083,8 @@ static int be_probe(struct pci_dev *pdev, const struct pci_device_id *pdev_id)
 	netif_napi_add(netdev, &pnob->napi, be_poll, 64);
 
 	/* if the rx_frag size if 2K, one page is shared as two RX frags */
-	pnob->rx_pg_shared = (pnob->rx_buf_size <= PAGE_SIZE / 2)? true : false;
+	pnob->rx_pg_shared =
+		(pnob->rx_buf_size <= PAGE_SIZE / 2) ? true : false;
 	if (pnob->rx_buf_size != rxbuf_size) {
 		printk(KERN_WARNING
 		       "Could not set Rx buffer size to %d. Using %d\n",

drivers/staging/benet/be_int.c

@@ -156,7 +156,8 @@ static inline int process_nic_rx_completion(struct be_net_object *pnob,
 	va = page_address(rx_page_info->page) + rx_page_info->page_offset;
 	prefetch(va);
 
-	skb->len = skb->data_len = n;
+	skb->len = n;
+	skb->data_len = n;
 	if (n <= BE_HDR_LEN) {
 		memcpy(skb->data, va, n);
 		put_page(rx_page_info->page);
@@ -717,7 +718,8 @@ irqreturn_t be_int(int irq, void *dev)
  */
 int be_poll(struct napi_struct *napi, int budget)
 {
-	struct be_net_object *pnob = container_of(napi, struct be_net_object, napi);
+	struct be_net_object *pnob =
+			container_of(napi, struct be_net_object, napi);
 	u32 work_done;
 
 	pnob->adapter->be_stat.bes_polls++;

drivers/staging/benet/be_netif.c

@@ -386,7 +386,8 @@ static void wrb_fill(struct ETH_WRB_AMAP *wrb, u64 addr, int len)
 static void wrb_fill_extra(struct ETH_WRB_AMAP *wrb, struct sk_buff *skb,
 			   struct be_net_object *pnob)
 {
-	wrb->dw[2] = wrb->dw[3] = 0;
+	wrb->dw[2] = 0;
+	wrb->dw[3] = 0;
 	AMAP_SET_BITS_PTR(ETH_WRB, crc, wrb, 1);
 	if (skb_shinfo(skb)->gso_segs > 1 && skb_shinfo(skb)->gso_size) {
 		AMAP_SET_BITS_PTR(ETH_WRB, lso, wrb, 1);

drivers/staging/benet/benet.h

@@ -280,7 +280,7 @@ struct be_adapter {
 
 	struct tasklet_struct sts_handler;
 	struct timer_list cq_timer;
-	spinlock_t int_lock;
+	spinlock_t int_lock;	/* to protect the isr field in adapter */
 
 	struct FWCMD_ETH_GET_STATISTICS *eth_statsp;
 	/*
@@ -300,7 +300,7 @@ struct be_adapter {
 	u32 max_rx_coal;
 	struct pci_dev *pdev;	/* Pointer to OS's PCI dvice */
 
-	spinlock_t txq_lock;
+	spinlock_t txq_lock;	/* to stop/wake queue based on tx_q_used */
 
 	u32 isr;		/* copy of Intr status reg. */
 

drivers/staging/benet/hwlib.h

@@ -39,28 +39,28 @@
  * in BladeEngine.
  */
 #define PD_READ(fo, field)	ioread32((fo)->db_va + \
-					offsetof(struct BE_PROTECTION_DOMAIN_DBMAP_AMAP, field)/8)
+		offsetof(struct BE_PROTECTION_DOMAIN_DBMAP_AMAP, field)/8)
 
 #define PD_WRITE(fo, field, val) iowrite32(val, (fo)->db_va + \
-					offsetof(struct BE_PROTECTION_DOMAIN_DBMAP_AMAP, field)/8)
+		offsetof(struct BE_PROTECTION_DOMAIN_DBMAP_AMAP, field)/8)
 
-#define CSR_READ(fo, field)		ioread32((fo)->csr_va + \
-					offsetof(struct BE_BLADE_ENGINE_CSRMAP_AMAP, field)/8)
+#define CSR_READ(fo, field)	ioread32((fo)->csr_va + \
+		offsetof(struct BE_BLADE_ENGINE_CSRMAP_AMAP, field)/8)
 
-#define CSR_WRITE(fo, field, val)	iowrite32(val, (fo)->csr_va +	\
-					offsetof(struct BE_BLADE_ENGINE_CSRMAP_AMAP, field)/8)
+#define CSR_WRITE(fo, field, val)	iowrite32(val, (fo)->csr_va + \
+		offsetof(struct BE_BLADE_ENGINE_CSRMAP_AMAP, field)/8)
 
 #define PCICFG0_READ(fo, field)	ioread32((fo)->pci_va + \
-					offsetof(struct BE_PCICFG0_CSRMAP_AMAP, field)/8)
+		offsetof(struct BE_PCICFG0_CSRMAP_AMAP, field)/8)
 
-#define PCICFG0_WRITE(fo, field, val)	iowrite32(val, (fo)->pci_va +	\
-					offsetof(struct BE_PCICFG0_CSRMAP_AMAP, field)/8)
+#define PCICFG0_WRITE(fo, field, val)	iowrite32(val, (fo)->pci_va + \
+		offsetof(struct BE_PCICFG0_CSRMAP_AMAP, field)/8)
 
-#define PCICFG1_READ(fo, field)		ioread32((fo)->pci_va + \
-					offsetof(struct BE_PCICFG1_CSRMAP_AMAP, field)/8)
+#define PCICFG1_READ(fo, field)	ioread32((fo)->pci_va + \
+		offsetof(struct BE_PCICFG1_CSRMAP_AMAP, field)/8)
 
-#define PCICFG1_WRITE(fo, field, val)	iowrite32(val, (fo)->pci_va +	\
-					offsetof(struct BE_PCICFG1_CSRMAP_AMAP, field)/8)
+#define PCICFG1_WRITE(fo, field, val)	iowrite32(val, (fo)->pci_va + \
+		offsetof(struct BE_PCICFG1_CSRMAP_AMAP, field)/8)
 
 #ifdef BE_DEBUG
 #define ASSERT(c)       BUG_ON(!(c));
@@ -118,14 +118,14 @@ static inline u32 be_subc(u32 a, u32 b, u32 max)
 {
 	ASSERT(a <= max && b <= max);
 	ASSERT(max > 0);
-	return (a >= b ? (a - b) : (max - b + a));
+	return a >= b ? (a - b) : (max - b + a);
 }
 
 static inline u32 be_addc(u32 a, u32 b, u32 max)
 {
 	ASSERT(a < max);
 	ASSERT(max > 0);
-	return ((max - a > b) ? (a + b) : (b + a - max));
+	return (max - a > b) ? (a + b) : (b + a - max);
 }
 
 /* descriptor for a physically contiguous memory used for ring */
@@ -174,7 +174,7 @@ struct mp_ring {
  */
 static inline u32 amap_mask(u32 bit_size)
 {
-    return (bit_size == 32 ? 0xFFFFFFFF : (1 << bit_size) - 1);
+	return bit_size == 32 ? 0xFFFFFFFF : (1 << bit_size) - 1;
 }
 
 #define AMAP_BIT_MASK(_struct_, field)       \
@@ -194,9 +194,9 @@ amap_set(void *ptr, u32 dw_offset, u32 mask, u32 offset, u32 value)
 }
 
 #define AMAP_SET_BITS_PTR(_struct_, field, _structPtr_, val)	\
-	amap_set(_structPtr_, AMAP_WORD_OFFSET(_struct_, field),	\
-		AMAP_BIT_MASK(_struct_, field),	AMAP_BIT_OFFSET(_struct_, field), val)
-
+	amap_set(_structPtr_, AMAP_WORD_OFFSET(_struct_, field),\
+		AMAP_BIT_MASK(_struct_, field),			\
+		AMAP_BIT_OFFSET(_struct_, field), val)
 /*
  * Non-optimized routine that gets the bits without knowing the correct DWORD.
  * e.g. fieldValue = AMAP_GET_BITS_PTR (struct, field1, &contextMemory);
@@ -207,13 +207,14 @@ amap_get(void *ptr, u32 dw_offset, u32 mask, u32 offset)
 	u32 *dw = (u32 *)ptr;
 	return mask & (*(dw + dw_offset) >> offset);
 }
-#define AMAP_GET_BITS_PTR(_struct_, field, _structPtr_)		\
+#define AMAP_GET_BITS_PTR(_struct_, field, _structPtr_)			\
 	amap_get(_structPtr_, AMAP_WORD_OFFSET(_struct_, field),	\
-		AMAP_BIT_MASK(_struct_, field),	AMAP_BIT_OFFSET(_struct_, field))
+		AMAP_BIT_MASK(_struct_, field),				\
+		AMAP_BIT_OFFSET(_struct_, field))
 
 /* Returns 0-31 representing bit offset within a DWORD of a bitfield. */
 #define AMAP_BIT_OFFSET(_struct_, field)                  \
-    (offsetof(struct BE_ ## _struct_ ## _AMAP, field) % 32)
+	(offsetof(struct BE_ ## _struct_ ## _AMAP, field) % 32)
 
 /* Returns 0-n representing DWORD offset of bitfield within the structure. */
 #define AMAP_WORD_OFFSET(_struct_, field)  \

drivers/staging/benet/mpu.c

@@ -942,7 +942,7 @@ be_mpu_init_mailbox(struct be_function_object *pfob, struct ring_desc *mailbox)
 	 */
 	{
 		u64 *endian_check = (u64 *) (pfob->mailbox.va +
-					offsetof(struct BE_MCC_MAILBOX_AMAP, wrb)/8);
+				offsetof(struct BE_MCC_MAILBOX_AMAP, wrb)/8);
 		*endian_check = 0xFF1234FFFF5678FFULL;
 	}