Commit a9ce1afb authored by Gregory CLEMENT's avatar Gregory CLEMENT Committed by Jason Cooper

ARM: mvebu: Fix the Aurora L2 cache node with the required cache-unified property

The L2 cache controller on the Armada 370 and Armada XP SoCs is a
unified cache. Moreover, the Aurora cache controller is compatible
with the L2x0 cache controller: the "cache-unified" property is
required by its binding.

This patch fixes the Aurora L2 cache node for the Armada 370 and
Armada XP SoCs by adding this property.
Reported-by: default avatarSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: default avatarGregory CLEMENT <gregory.clement@free-electrons.com>
Acked-by: default avatarSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Link: https://lkml.kernel.org/r/1412588276-4514-1-git-send-email-gregory.clement@free-electrons.comSigned-off-by: default avatarJason Cooper <jason@lakedaemon.net>
parent f114040e
...@@ -95,6 +95,7 @@ L2: l2-cache { ...@@ -95,6 +95,7 @@ L2: l2-cache {
compatible = "marvell,aurora-outer-cache"; compatible = "marvell,aurora-outer-cache";
reg = <0x08000 0x1000>; reg = <0x08000 0x1000>;
cache-id-part = <0x100>; cache-id-part = <0x100>;
cache-unified;
wt-override; wt-override;
}; };
......
...@@ -39,6 +39,7 @@ L2: l2-cache { ...@@ -39,6 +39,7 @@ L2: l2-cache {
compatible = "marvell,aurora-system-cache"; compatible = "marvell,aurora-system-cache";
reg = <0x08000 0x1000>; reg = <0x08000 0x1000>;
cache-id-part = <0x100>; cache-id-part = <0x100>;
cache-unified;
wt-override; wt-override;
}; };
......
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