Commit a9dd3865 authored by Russell King's avatar Russell King

Merge branch 'for-arm-soc' into for-next

parents 27a513ca 2678bb9f
...@@ -70,7 +70,7 @@ &mmc_0 { ...@@ -70,7 +70,7 @@ &mmc_0 {
broken-cd; broken-cd;
bypass-smu; bypass-smu;
cap-mmc-highspeed; cap-mmc-highspeed;
supports-hs200-mode; /* 200 Mhz */ supports-hs200-mode; /* 200 MHz */
card-detect-delay = <200>; card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <0 4>; samsung,dw-mshc-sdr-timing = <0 4>;
......
...@@ -66,7 +66,7 @@ OMAP3_CORE1_IOPAD(0x217a, PIN_OUTPUT | MUX_MODE4) /* uart2_rx.gpio_147 */ ...@@ -66,7 +66,7 @@ OMAP3_CORE1_IOPAD(0x217a, PIN_OUTPUT | MUX_MODE4) /* uart2_rx.gpio_147 */
otg_drv_vbus: pinmux_otg_drv_vbus { otg_drv_vbus: pinmux_otg_drv_vbus {
pinctrl-single,pins = < pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x2210, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii_50Mhz_clk.usb0_drvvbus */ OMAP3_CORE1_IOPAD(0x2210, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii_50MHz_clk.usb0_drvvbus */
>; >;
}; };
......
...@@ -7,6 +7,7 @@ struct sleep_save_sp { ...@@ -7,6 +7,7 @@ struct sleep_save_sp {
}; };
extern void cpu_resume(void); extern void cpu_resume(void);
extern void cpu_resume_arm(void);
extern int cpu_suspend(unsigned long, int (*)(unsigned long)); extern int cpu_suspend(unsigned long, int (*)(unsigned long));
#endif #endif
...@@ -118,6 +118,16 @@ ENDPROC(cpu_resume_after_mmu) ...@@ -118,6 +118,16 @@ ENDPROC(cpu_resume_after_mmu)
.text .text
.align .align
#ifdef CONFIG_MMU
.arm
ENTRY(cpu_resume_arm)
THUMB( adr r9, BSYM(1f) ) @ Kernel is entered in ARM.
THUMB( bx r9 ) @ If this is a Thumb-2 kernel,
THUMB( .thumb ) @ switch to Thumb now.
THUMB(1: )
#endif
ENTRY(cpu_resume) ENTRY(cpu_resume)
ARM_BE8(setend be) @ ensure we are in BE mode ARM_BE8(setend be) @ ensure we are in BE mode
#ifdef CONFIG_ARM_VIRT_EXT #ifdef CONFIG_ARM_VIRT_EXT
...@@ -150,6 +160,10 @@ THUMB( mov sp, r2 ) ...@@ -150,6 +160,10 @@ THUMB( mov sp, r2 )
THUMB( bx r3 ) THUMB( bx r3 )
ENDPROC(cpu_resume) ENDPROC(cpu_resume)
#ifdef CONFIG_MMU
ENDPROC(cpu_resume_arm)
#endif
.align 2 .align 2
_sleep_save_sp: _sleep_save_sp:
.long sleep_save_sp - . .long sleep_save_sp - .
......
...@@ -43,5 +43,5 @@ obj-$(CONFIG_ARCH_BCM_63XX) := bcm63xx.o ...@@ -43,5 +43,5 @@ obj-$(CONFIG_ARCH_BCM_63XX) := bcm63xx.o
ifeq ($(CONFIG_ARCH_BRCMSTB),y) ifeq ($(CONFIG_ARCH_BRCMSTB),y)
CFLAGS_platsmp-brcmstb.o += -march=armv7-a CFLAGS_platsmp-brcmstb.o += -march=armv7-a
obj-y += brcmstb.o obj-y += brcmstb.o
obj-$(CONFIG_SMP) += headsmp-brcmstb.o platsmp-brcmstb.o obj-$(CONFIG_SMP) += platsmp-brcmstb.o
endif endif
/*
* Copyright (C) 2013-2014 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __BRCMSTB_H__
#define __BRCMSTB_H__
void brcmstb_secondary_startup(void);
#endif /* __BRCMSTB_H__ */
/*
* SMP boot code for secondary CPUs
* Based on arch/arm/mach-tegra/headsmp.S
*
* Copyright (C) 2010 NVIDIA, Inc.
* Copyright (C) 2013-2014 Broadcom Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <asm/assembler.h>
#include <linux/linkage.h>
#include <linux/init.h>
.section ".text.head", "ax"
ENTRY(brcmstb_secondary_startup)
/*
* Ensure CPU is in a sane state by disabling all IRQs and switching
* into SVC mode.
*/
setmode PSR_I_BIT | PSR_F_BIT | SVC_MODE, r0
bl v7_invalidate_l1
b secondary_startup
ENDPROC(brcmstb_secondary_startup)
...@@ -30,8 +30,6 @@ ...@@ -30,8 +30,6 @@
#include <asm/mach-types.h> #include <asm/mach-types.h>
#include <asm/smp_plat.h> #include <asm/smp_plat.h>
#include "brcmstb.h"
enum { enum {
ZONE_MAN_CLKEN_MASK = BIT(0), ZONE_MAN_CLKEN_MASK = BIT(0),
ZONE_MAN_RESET_CNTL_MASK = BIT(1), ZONE_MAN_RESET_CNTL_MASK = BIT(1),
...@@ -153,7 +151,7 @@ static void brcmstb_cpu_boot(u32 cpu) ...@@ -153,7 +151,7 @@ static void brcmstb_cpu_boot(u32 cpu)
* Set the reset vector to point to the secondary_startup * Set the reset vector to point to the secondary_startup
* routine * routine
*/ */
cpu_set_boot_addr(cpu, virt_to_phys(brcmstb_secondary_startup)); cpu_set_boot_addr(cpu, virt_to_phys(secondary_startup));
/* Unhalt the cpu */ /* Unhalt the cpu */
cpu_rst_cfg_set(cpu, 0); cpu_rst_cfg_set(cpu, 0);
......
...@@ -12,12 +12,6 @@ ...@@ -12,12 +12,6 @@
#include <linux/init.h> #include <linux/init.h>
#include <asm/assembler.h> #include <asm/assembler.h>
ENTRY(berlin_secondary_startup)
ARM_BE8(setend be)
bl v7_invalidate_l1
b secondary_startup
ENDPROC(berlin_secondary_startup)
/* /*
* If the following instruction is set in the reset exception vector, CPUs * If the following instruction is set in the reset exception vector, CPUs
* will fetch the value of the software reset address vector when being * will fetch the value of the software reset address vector when being
......
...@@ -22,7 +22,6 @@ ...@@ -22,7 +22,6 @@
#define RESET_VECT 0x00 #define RESET_VECT 0x00
#define SW_RESET_ADDR 0x94 #define SW_RESET_ADDR 0x94
extern void berlin_secondary_startup(void);
extern u32 boot_inst; extern u32 boot_inst;
static void __iomem *cpu_ctrl; static void __iomem *cpu_ctrl;
...@@ -85,7 +84,7 @@ static void __init berlin_smp_prepare_cpus(unsigned int max_cpus) ...@@ -85,7 +84,7 @@ static void __init berlin_smp_prepare_cpus(unsigned int max_cpus)
* Write the secondary startup address into the SW reset address * Write the secondary startup address into the SW reset address
* vector. This is used by boot_inst. * vector. This is used by boot_inst.
*/ */
writel(virt_to_phys(berlin_secondary_startup), vectors_base + SW_RESET_ADDR); writel(virt_to_phys(secondary_startup), vectors_base + SW_RESET_ADDR);
iounmap(vectors_base); iounmap(vectors_base);
unmap_scu: unmap_scu:
......
...@@ -36,7 +36,7 @@ extern void __iomem *da8xx_syscfg1_base; ...@@ -36,7 +36,7 @@ extern void __iomem *da8xx_syscfg1_base;
/* /*
* If the DA850/OMAP-L138/AM18x SoC on board is of a higher speed grade * If the DA850/OMAP-L138/AM18x SoC on board is of a higher speed grade
* (than the regular 300Mhz variant), the board code should set this up * (than the regular 300MHz variant), the board code should set this up
* with the supported speed before calling da850_register_cpufreq(). * with the supported speed before calling da850_register_cpufreq().
*/ */
extern unsigned int da850_max_speed; extern unsigned int da850_max_speed;
......
...@@ -6,4 +6,4 @@ CFLAGS_platmcpm.o := -march=armv7-a ...@@ -6,4 +6,4 @@ CFLAGS_platmcpm.o := -march=armv7-a
obj-y += hisilicon.o obj-y += hisilicon.o
obj-$(CONFIG_MCPM) += platmcpm.o obj-$(CONFIG_MCPM) += platmcpm.o
obj-$(CONFIG_SMP) += platsmp.o hotplug.o headsmp.o obj-$(CONFIG_SMP) += platsmp.o hotplug.o
...@@ -12,7 +12,6 @@ extern void hi3xxx_cpu_die(unsigned int cpu); ...@@ -12,7 +12,6 @@ extern void hi3xxx_cpu_die(unsigned int cpu);
extern int hi3xxx_cpu_kill(unsigned int cpu); extern int hi3xxx_cpu_kill(unsigned int cpu);
extern void hi3xxx_set_cpu(int cpu, bool enable); extern void hi3xxx_set_cpu(int cpu, bool enable);
extern void hisi_secondary_startup(void);
extern struct smp_operations hix5hd2_smp_ops; extern struct smp_operations hix5hd2_smp_ops;
extern void hix5hd2_set_cpu(int cpu, bool enable); extern void hix5hd2_set_cpu(int cpu, bool enable);
extern void hix5hd2_cpu_die(unsigned int cpu); extern void hix5hd2_cpu_die(unsigned int cpu);
......
/*
* Copyright (c) 2014 Hisilicon Limited.
* Copyright (c) 2014 Linaro Ltd.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/linkage.h>
#include <linux/init.h>
__CPUINIT
ENTRY(hisi_secondary_startup)
bl v7_invalidate_l1
b secondary_startup
...@@ -118,7 +118,7 @@ static int hix5hd2_boot_secondary(unsigned int cpu, struct task_struct *idle) ...@@ -118,7 +118,7 @@ static int hix5hd2_boot_secondary(unsigned int cpu, struct task_struct *idle)
{ {
phys_addr_t jumpaddr; phys_addr_t jumpaddr;
jumpaddr = virt_to_phys(hisi_secondary_startup); jumpaddr = virt_to_phys(secondary_startup);
hix5hd2_set_scu_boot_addr(HIX5HD2_BOOT_ADDRESS, jumpaddr); hix5hd2_set_scu_boot_addr(HIX5HD2_BOOT_ADDRESS, jumpaddr);
hix5hd2_set_cpu(cpu, true); hix5hd2_set_cpu(cpu, true);
arch_send_wakeup_ipi_mask(cpumask_of(cpu)); arch_send_wakeup_ipi_mask(cpumask_of(cpu));
...@@ -156,7 +156,7 @@ static int hip01_boot_secondary(unsigned int cpu, struct task_struct *idle) ...@@ -156,7 +156,7 @@ static int hip01_boot_secondary(unsigned int cpu, struct task_struct *idle)
struct device_node *node; struct device_node *node;
jumpaddr = virt_to_phys(hisi_secondary_startup); jumpaddr = virt_to_phys(secondary_startup);
hip01_set_boot_addr(HIP01_BOOT_ADDRESS, jumpaddr); hip01_set_boot_addr(HIP01_BOOT_ADDRESS, jumpaddr);
node = of_find_compatible_node(NULL, NULL, "hisilicon,hip01-sysctrl"); node = of_find_compatible_node(NULL, NULL, "hisilicon,hip01-sysctrl");
......
...@@ -216,7 +216,7 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) ...@@ -216,7 +216,7 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
clks[IMX6SX_CLK_USBPHY1_GATE] = imx_clk_gate("usbphy1_gate", "dummy", base + 0x10, 6); clks[IMX6SX_CLK_USBPHY1_GATE] = imx_clk_gate("usbphy1_gate", "dummy", base + 0x10, 6);
clks[IMX6SX_CLK_USBPHY2_GATE] = imx_clk_gate("usbphy2_gate", "dummy", base + 0x20, 6); clks[IMX6SX_CLK_USBPHY2_GATE] = imx_clk_gate("usbphy2_gate", "dummy", base + 0x20, 6);
/* FIXME 100Mhz is used for pcie ref for all imx6 pcie, excepted imx6q */ /* FIXME 100MHz is used for pcie ref for all imx6 pcie, excepted imx6q */
clks[IMX6SX_CLK_PCIE_REF] = imx_clk_fixed_factor("pcie_ref", "pll6_enet", 1, 5); clks[IMX6SX_CLK_PCIE_REF] = imx_clk_fixed_factor("pcie_ref", "pll6_enet", 1, 5);
clks[IMX6SX_CLK_PCIE_REF_125M] = imx_clk_gate("pcie_ref_125m", "pcie_ref", base + 0xe0, 19); clks[IMX6SX_CLK_PCIE_REF_125M] = imx_clk_gate("pcie_ref_125m", "pcie_ref", base + 0xe0, 19);
...@@ -520,7 +520,7 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) ...@@ -520,7 +520,7 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
pr_err("Failed to set pcie parent clk.\n"); pr_err("Failed to set pcie parent clk.\n");
/* /*
* Init enet system AHB clock, set to 200Mhz * Init enet system AHB clock, set to 200MHz
* pll2_pfd2_396m-> ENET_PODF-> ENET_AHB * pll2_pfd2_396m-> ENET_PODF-> ENET_AHB
*/ */
clk_set_parent(clks[IMX6SX_CLK_ENET_PRE_SEL], clks[IMX6SX_CLK_PLL2_PFD2]); clk_set_parent(clks[IMX6SX_CLK_ENET_PRE_SEL], clks[IMX6SX_CLK_PLL2_PFD2]);
......
...@@ -25,7 +25,6 @@ diag_reg_offset: ...@@ -25,7 +25,6 @@ diag_reg_offset:
.endm .endm
ENTRY(v7_secondary_startup) ENTRY(v7_secondary_startup)
bl v7_invalidate_l1
set_diag_reg set_diag_reg
b secondary_startup b secondary_startup
ENDPROC(v7_secondary_startup) ENDPROC(v7_secondary_startup)
...@@ -42,7 +42,7 @@ static inline unsigned long iop13xx_core_freq(void) ...@@ -42,7 +42,7 @@ static inline unsigned long iop13xx_core_freq(void)
case IOP13XX_CORE_FREQ_1200: case IOP13XX_CORE_FREQ_1200:
return 1200000000; return 1200000000;
default: default:
printk("%s: warning unknown frequency, defaulting to 800Mhz\n", printk("%s: warning unknown frequency, defaulting to 800MHz\n",
__func__); __func__);
} }
......
...@@ -74,7 +74,7 @@ extern unsigned long ixp4xx_exp_bus_size; ...@@ -74,7 +74,7 @@ extern unsigned long ixp4xx_exp_bus_size;
/* /*
* Clock Speed Definitions. * Clock Speed Definitions.
*/ */
#define IXP4XX_PERIPHERAL_BUS_CLOCK (66) /* 66Mhzi APB BUS */ #define IXP4XX_PERIPHERAL_BUS_CLOCK (66) /* 66MHzi APB BUS */
#define IXP4XX_UART_XTAL 14745600 #define IXP4XX_UART_XTAL 14745600
/* /*
......
...@@ -17,7 +17,7 @@ ...@@ -17,7 +17,7 @@
#include <asm/sizes.h> #include <asm/sizes.h>
/* /*
* Clocks are derived from MCLK, which is 25Mhz * Clocks are derived from MCLK, which is 25MHz
*/ */
#define KS8695_CLOCK_RATE 25000000 #define KS8695_CLOCK_RATE 25000000
......
...@@ -21,7 +21,6 @@ ...@@ -21,7 +21,6 @@
ENTRY(mvebu_cortex_a9_secondary_startup) ENTRY(mvebu_cortex_a9_secondary_startup)
ARM_BE8(setend be) ARM_BE8(setend be)
bl v7_invalidate_l1
bl armada_38x_scu_power_up bl armada_38x_scu_power_up
b secondary_startup b secondary_startup
ENDPROC(mvebu_cortex_a9_secondary_startup) ENDPROC(mvebu_cortex_a9_secondary_startup)
...@@ -216,11 +216,11 @@ static void omap2_onenand_calc_sync_timings(struct gpmc_timings *t, ...@@ -216,11 +216,11 @@ static void omap2_onenand_calc_sync_timings(struct gpmc_timings *t,
div = gpmc_calc_divider(min_gpmc_clk_period); div = gpmc_calc_divider(min_gpmc_clk_period);
gpmc_clk_ns = gpmc_ticks_to_ns(div); gpmc_clk_ns = gpmc_ticks_to_ns(div);
if (gpmc_clk_ns < 15) /* >66Mhz */ if (gpmc_clk_ns < 15) /* >66MHz */
onenand_flags |= ONENAND_FLAG_HF; onenand_flags |= ONENAND_FLAG_HF;
else else
onenand_flags &= ~ONENAND_FLAG_HF; onenand_flags &= ~ONENAND_FLAG_HF;
if (gpmc_clk_ns < 12) /* >83Mhz */ if (gpmc_clk_ns < 12) /* >83MHz */
onenand_flags |= ONENAND_FLAG_VHF; onenand_flags |= ONENAND_FLAG_VHF;
else else
onenand_flags &= ~ONENAND_FLAG_VHF; onenand_flags &= ~ONENAND_FLAG_VHF;
......
...@@ -70,7 +70,7 @@ static void omap_hsmmc1_before_set_reg(struct device *dev, ...@@ -70,7 +70,7 @@ static void omap_hsmmc1_before_set_reg(struct device *dev,
reg = omap_ctrl_readl(control_pbias_offset); reg = omap_ctrl_readl(control_pbias_offset);
if (cpu_is_omap3630()) { if (cpu_is_omap3630()) {
/* Set MMC I/O to 52Mhz */ /* Set MMC I/O to 52MHz */
prog_io = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1); prog_io = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1);
prog_io |= OMAP3630_PRG_SDMMC1_SPEEDCTRL; prog_io |= OMAP3630_PRG_SDMMC1_SPEEDCTRL;
omap_ctrl_writel(prog_io, OMAP343X_CONTROL_PROG_IO1); omap_ctrl_writel(prog_io, OMAP343X_CONTROL_PROG_IO1);
......
...@@ -116,7 +116,7 @@ const struct prcm_config omap2430_rate_table[] = { ...@@ -116,7 +116,7 @@ const struct prcm_config omap2430_rate_table[] = {
RATE_IN_243X}, RATE_IN_243X},
/* PRCM-boot/bypass */ /* PRCM-boot/bypass */
{S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL, /* 13Mhz */ {S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL, /* 13MHz */
RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL, RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL, RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL,
MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL, MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
...@@ -124,7 +124,7 @@ const struct prcm_config omap2430_rate_table[] = { ...@@ -124,7 +124,7 @@ const struct prcm_config omap2430_rate_table[] = {
RATE_IN_243X}, RATE_IN_243X},
/* PRCM-boot/bypass */ /* PRCM-boot/bypass */
{S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL, /* 12Mhz */ {S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL, /* 12MHz */
RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL, RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL, RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL,
MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL, MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
......
...@@ -164,6 +164,6 @@ void omap2xxx_sdrc_init_params(u32 force_lock_to_unlock_mode) ...@@ -164,6 +164,6 @@ void omap2xxx_sdrc_init_params(u32 force_lock_to_unlock_mode)
mem_timings.slow_dll_ctrl |= mem_timings.slow_dll_ctrl |=
((mem_timings.fast_dll_ctrl & 0xF) | (1 << 2)); ((mem_timings.fast_dll_ctrl & 0xF) | (1 << 2));
/* 90 degree phase for anything below 133Mhz + disable DLL filter */ /* 90 degree phase for anything below 133MHz + disable DLL filter */
mem_timings.slow_dll_ctrl |= ((1 << 1) | (3 << 8)); mem_timings.slow_dll_ctrl |= ((1 << 1) | (3 << 8));
} }
...@@ -64,7 +64,7 @@ ENTRY(omap242x_sram_ddr_init) ...@@ -64,7 +64,7 @@ ENTRY(omap242x_sram_ddr_init)
mvn r9, #0x4 @ mask to get clear bit2 mvn r9, #0x4 @ mask to get clear bit2
and r10, r10, r9 @ clear bit2 for lock mode. and r10, r10, r9 @ clear bit2 for lock mode.
orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos) orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos)
orr r10, r10, #0x2 @ 90 degree phase for all below 133Mhz orr r10, r10, #0x2 @ 90 degree phase for all below 133MHz
str r10, [r11] @ commit to DLLA_CTRL str r10, [r11] @ commit to DLLA_CTRL
bl i_dll_wait @ wait for dll to lock bl i_dll_wait @ wait for dll to lock
......
...@@ -64,7 +64,7 @@ ENTRY(omap243x_sram_ddr_init) ...@@ -64,7 +64,7 @@ ENTRY(omap243x_sram_ddr_init)
mvn r9, #0x4 @ mask to get clear bit2 mvn r9, #0x4 @ mask to get clear bit2
and r10, r10, r9 @ clear bit2 for lock mode. and r10, r10, r9 @ clear bit2 for lock mode.
orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos) orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos)
orr r10, r10, #0x2 @ 90 degree phase for all below 133Mhz orr r10, r10, #0x2 @ 90 degree phase for all below 133MHz
str r10, [r11] @ commit to DLLA_CTRL str r10, [r11] @ commit to DLLA_CTRL
bl i_dll_wait @ wait for dll to lock bl i_dll_wait @ wait for dll to lock
......
...@@ -15,7 +15,6 @@ ...@@ -15,7 +15,6 @@
* ready for them to initialise. * ready for them to initialise.
*/ */
ENTRY(sirfsoc_secondary_startup) ENTRY(sirfsoc_secondary_startup)
bl v7_invalidate_l1
mrc p15, 0, r0, c0, c0, 5 mrc p15, 0, r0, c0, c0, 5
and r0, r0, #15 and r0, r0, #15
adr r4, 1f adr r4, 1f
......
...@@ -28,7 +28,7 @@ ...@@ -28,7 +28,7 @@
static void isp116x_pfm_delay(struct device *dev, int delay) static void isp116x_pfm_delay(struct device *dev, int delay)
{ {
/* 400Mhz PXA2 = 2.5ns / instruction */ /* 400MHz PXA2 = 2.5ns / instruction */
int cyc = delay / 10; int cyc = delay / 10;
......
...@@ -17,4 +17,3 @@ extern char rockchip_secondary_trampoline; ...@@ -17,4 +17,3 @@ extern char rockchip_secondary_trampoline;
extern char rockchip_secondary_trampoline_end; extern char rockchip_secondary_trampoline_end;
extern unsigned long rockchip_boot_fn; extern unsigned long rockchip_boot_fn;
extern void rockchip_secondary_startup(void);
...@@ -15,14 +15,6 @@ ...@@ -15,14 +15,6 @@
#include <linux/linkage.h> #include <linux/linkage.h>
#include <linux/init.h> #include <linux/init.h>
ENTRY(rockchip_secondary_startup)
mrc p15, 0, r0, c0, c0, 0 @ read main ID register
ldr r1, =0x00000c09 @ Cortex-A9 primary part number
teq r0, r1
beq v7_invalidate_l1
b secondary_startup
ENDPROC(rockchip_secondary_startup)
ENTRY(rockchip_secondary_trampoline) ENTRY(rockchip_secondary_trampoline)
ldr pc, 1f ldr pc, 1f
ENDPROC(rockchip_secondary_trampoline) ENDPROC(rockchip_secondary_trampoline)
......
...@@ -149,8 +149,7 @@ static int __cpuinit rockchip_boot_secondary(unsigned int cpu, ...@@ -149,8 +149,7 @@ static int __cpuinit rockchip_boot_secondary(unsigned int cpu,
* sram_base_addr + 8: start address for pc * sram_base_addr + 8: start address for pc
* */ * */
udelay(10); udelay(10);
writel(virt_to_phys(rockchip_secondary_startup), writel(virt_to_phys(secondary_startup), sram_base_addr + 8);
sram_base_addr + 8);
writel(0xDEADBEAF, sram_base_addr + 4); writel(0xDEADBEAF, sram_base_addr + 4);
dsb_sev(); dsb_sev();
} }
...@@ -189,7 +188,7 @@ static int __init rockchip_smp_prepare_sram(struct device_node *node) ...@@ -189,7 +188,7 @@ static int __init rockchip_smp_prepare_sram(struct device_node *node)
} }
/* set the boot function for the sram code */ /* set the boot function for the sram code */
rockchip_boot_fn = virt_to_phys(rockchip_secondary_startup); rockchip_boot_fn = virt_to_phys(secondary_startup);
/* copy the trampoline to sram, that runs during startup of the core */ /* copy the trampoline to sram, that runs during startup of the core */
memcpy(sram_base_addr, &rockchip_secondary_trampoline, trampoline_sz); memcpy(sram_base_addr, &rockchip_secondary_trampoline, trampoline_sz);
......
...@@ -14,7 +14,6 @@ extern void shmobile_smp_sleep(void); ...@@ -14,7 +14,6 @@ extern void shmobile_smp_sleep(void);
extern void shmobile_smp_hook(unsigned int cpu, unsigned long fn, extern void shmobile_smp_hook(unsigned int cpu, unsigned long fn,
unsigned long arg); unsigned long arg);
extern int shmobile_smp_cpu_disable(unsigned int cpu); extern int shmobile_smp_cpu_disable(unsigned int cpu);
extern void shmobile_invalidate_start(void);
extern void shmobile_boot_scu(void); extern void shmobile_boot_scu(void);
extern void shmobile_smp_scu_prepare_cpus(unsigned int max_cpus); extern void shmobile_smp_scu_prepare_cpus(unsigned int max_cpus);
extern void shmobile_smp_scu_cpu_die(unsigned int cpu); extern void shmobile_smp_scu_cpu_die(unsigned int cpu);
......
...@@ -22,7 +22,7 @@ ...@@ -22,7 +22,7 @@
* Boot code for secondary CPUs. * Boot code for secondary CPUs.
* *
* First we turn on L1 cache coherency for our CPU. Then we jump to * First we turn on L1 cache coherency for our CPU. Then we jump to
* shmobile_invalidate_start that invalidates the cache and hands over control * secondary_startup that invalidates the cache and hands over control
* to the common ARM startup code. * to the common ARM startup code.
*/ */
ENTRY(shmobile_boot_scu) ENTRY(shmobile_boot_scu)
...@@ -36,7 +36,7 @@ ENTRY(shmobile_boot_scu) ...@@ -36,7 +36,7 @@ ENTRY(shmobile_boot_scu)
bic r2, r2, r3 @ Clear bits of our CPU (Run Mode) bic r2, r2, r3 @ Clear bits of our CPU (Run Mode)
str r2, [r0, #8] @ write back str r2, [r0, #8] @ write back
b shmobile_invalidate_start b secondary_startup
ENDPROC(shmobile_boot_scu) ENDPROC(shmobile_boot_scu)
.text .text
......
...@@ -16,13 +16,6 @@ ...@@ -16,13 +16,6 @@
#include <asm/assembler.h> #include <asm/assembler.h>
#include <asm/memory.h> #include <asm/memory.h>
#ifdef CONFIG_SMP
ENTRY(shmobile_invalidate_start)
bl v7_invalidate_l1
b secondary_startup
ENDPROC(shmobile_invalidate_start)
#endif
/* /*
* Reset vector for secondary CPUs. * Reset vector for secondary CPUs.
* This will be mapped at address 0 by SBAR register. * This will be mapped at address 0 by SBAR register.
......
...@@ -133,7 +133,7 @@ void __init shmobile_smp_apmu_prepare_cpus(unsigned int max_cpus, ...@@ -133,7 +133,7 @@ void __init shmobile_smp_apmu_prepare_cpus(unsigned int max_cpus,
int shmobile_smp_apmu_boot_secondary(unsigned int cpu, struct task_struct *idle) int shmobile_smp_apmu_boot_secondary(unsigned int cpu, struct task_struct *idle)
{ {
/* For this particular CPU register boot vector */ /* For this particular CPU register boot vector */
shmobile_smp_hook(cpu, virt_to_phys(shmobile_invalidate_start), 0); shmobile_smp_hook(cpu, virt_to_phys(secondary_startup), 0);
return apmu_wrap(cpu, apmu_power_on); return apmu_wrap(cpu, apmu_power_on);
} }
......
...@@ -31,7 +31,6 @@ ...@@ -31,7 +31,6 @@
#define RSTMGR_MPUMODRST_CPU1 0x2 /* CPU1 Reset */ #define RSTMGR_MPUMODRST_CPU1 0x2 /* CPU1 Reset */
extern void socfpga_secondary_startup(void);
extern void __iomem *socfpga_scu_base_addr; extern void __iomem *socfpga_scu_base_addr;
extern void socfpga_init_clocks(void); extern void socfpga_init_clocks(void);
......
...@@ -30,8 +30,3 @@ ENTRY(secondary_trampoline) ...@@ -30,8 +30,3 @@ ENTRY(secondary_trampoline)
1: .long . 1: .long .
.long socfpga_cpu1start_addr .long socfpga_cpu1start_addr
ENTRY(secondary_trampoline_end) ENTRY(secondary_trampoline_end)
ENTRY(socfpga_secondary_startup)
bl v7_invalidate_l1
b secondary_startup
ENDPROC(socfpga_secondary_startup)
...@@ -40,7 +40,7 @@ static int socfpga_boot_secondary(unsigned int cpu, struct task_struct *idle) ...@@ -40,7 +40,7 @@ static int socfpga_boot_secondary(unsigned int cpu, struct task_struct *idle)
memcpy(phys_to_virt(0), &secondary_trampoline, trampoline_size); memcpy(phys_to_virt(0), &secondary_trampoline, trampoline_size);
writel(virt_to_phys(socfpga_secondary_startup), writel(virt_to_phys(secondary_startup),
sys_manager_base_addr + (socfpga_cpu1start_addr & 0x000000ff)); sys_manager_base_addr + (socfpga_cpu1start_addr & 0x000000ff));
flush_cache_all(); flush_cache_all();
......
...@@ -19,7 +19,7 @@ obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += pm-tegra30.o ...@@ -19,7 +19,7 @@ obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += pm-tegra30.o
ifeq ($(CONFIG_CPU_IDLE),y) ifeq ($(CONFIG_CPU_IDLE),y)
obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += cpuidle-tegra30.o obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += cpuidle-tegra30.o
endif endif
obj-$(CONFIG_SMP) += platsmp.o headsmp.o obj-$(CONFIG_SMP) += platsmp.o
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
obj-$(CONFIG_ARCH_TEGRA_114_SOC) += sleep-tegra30.o obj-$(CONFIG_ARCH_TEGRA_114_SOC) += sleep-tegra30.o
......
#include <linux/linkage.h>
#include <linux/init.h>
#include "sleep.h"
.section ".text.head", "ax"
ENTRY(tegra_secondary_startup)
check_cpu_part_num 0xc09, r8, r9
bleq v7_invalidate_l1
b secondary_startup
ENDPROC(tegra_secondary_startup)
...@@ -94,7 +94,7 @@ void __init tegra_cpu_reset_handler_init(void) ...@@ -94,7 +94,7 @@ void __init tegra_cpu_reset_handler_init(void)
__tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_PRESENT] = __tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_PRESENT] =
*((u32 *)cpu_possible_mask); *((u32 *)cpu_possible_mask);
__tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_SECONDARY] = __tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_SECONDARY] =
virt_to_phys((void *)tegra_secondary_startup); virt_to_phys((void *)secondary_startup);
#endif #endif
#ifdef CONFIG_PM_SLEEP #ifdef CONFIG_PM_SLEEP
......
...@@ -36,7 +36,6 @@ extern unsigned long __tegra_cpu_reset_handler_data[TEGRA_RESET_DATA_SIZE]; ...@@ -36,7 +36,6 @@ extern unsigned long __tegra_cpu_reset_handler_data[TEGRA_RESET_DATA_SIZE];
void __tegra_cpu_reset_handler_start(void); void __tegra_cpu_reset_handler_start(void);
void __tegra_cpu_reset_handler(void); void __tegra_cpu_reset_handler(void);
void __tegra_cpu_reset_handler_end(void); void __tegra_cpu_reset_handler_end(void);
void tegra_secondary_startup(void);
#ifdef CONFIG_PM_SLEEP #ifdef CONFIG_PM_SLEEP
#define tegra_cpu_lp1_mask \ #define tegra_cpu_lp1_mask \
......
...@@ -17,8 +17,6 @@ ...@@ -17,8 +17,6 @@
#ifndef __MACH_ZYNQ_COMMON_H__ #ifndef __MACH_ZYNQ_COMMON_H__
#define __MACH_ZYNQ_COMMON_H__ #define __MACH_ZYNQ_COMMON_H__
void zynq_secondary_startup(void);
extern int zynq_slcr_init(void); extern int zynq_slcr_init(void);
extern int zynq_early_slcr_init(void); extern int zynq_early_slcr_init(void);
extern void zynq_slcr_system_reset(void); extern void zynq_slcr_system_reset(void);
......
...@@ -22,8 +22,3 @@ zynq_secondary_trampoline_jump: ...@@ -22,8 +22,3 @@ zynq_secondary_trampoline_jump:
.globl zynq_secondary_trampoline_end .globl zynq_secondary_trampoline_end
zynq_secondary_trampoline_end: zynq_secondary_trampoline_end:
ENDPROC(zynq_secondary_trampoline) ENDPROC(zynq_secondary_trampoline)
ENTRY(zynq_secondary_startup)
bl v7_invalidate_l1
b secondary_startup
ENDPROC(zynq_secondary_startup)
...@@ -87,10 +87,9 @@ int zynq_cpun_start(u32 address, int cpu) ...@@ -87,10 +87,9 @@ int zynq_cpun_start(u32 address, int cpu)
} }
EXPORT_SYMBOL(zynq_cpun_start); EXPORT_SYMBOL(zynq_cpun_start);
static int zynq_boot_secondary(unsigned int cpu, static int zynq_boot_secondary(unsigned int cpu, struct task_struct *idle)
struct task_struct *idle)
{ {
return zynq_cpun_start(virt_to_phys(zynq_secondary_startup), cpu); return zynq_cpun_start(virt_to_phys(secondary_startup), cpu);
} }
/* /*
......
...@@ -414,7 +414,7 @@ __v7_pj4b_setup: ...@@ -414,7 +414,7 @@ __v7_pj4b_setup:
__v7_setup: __v7_setup:
adr r12, __v7_setup_stack @ the local stack adr r12, __v7_setup_stack @ the local stack
stmia r12, {r0-r5, r7, r9, r11, lr} stmia r12, {r0-r5, r7, r9, r11, lr}
bl v7_flush_dcache_louis bl v7_invalidate_l1
ldmia r12, {r0-r5, r7, r9, r11, lr} ldmia r12, {r0-r5, r7, r9, r11, lr}
and r0, r9, #0xff000000 @ ARM? and r0, r9, #0xff000000 @ ARM?
......
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