Commit aa55f601 authored by Maciej W. Rozycki's avatar Maciej W. Rozycki Committed by Greg Kroah-Hartman

MIPS: Actually decode JALX in `__compute_return_epc_for_insn'

commit a9db101b upstream.

Complement commit fb6883e5 ("MIPS: microMIPS: Support handling of
delay slots.") and actually decode the regular MIPS JALX major
instruction opcode, the handling of which has been added with the said
commit for EPC calculation in `__compute_return_epc_for_insn'.

Fixes: fb6883e5 ("MIPS: microMIPS: Support handling of delay slots.")
Signed-off-by: default avatarMaciej W. Rozycki <macro@imgtec.com>
Cc: James Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/16394/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent af0a820b
...@@ -556,6 +556,7 @@ int __compute_return_epc_for_insn(struct pt_regs *regs, ...@@ -556,6 +556,7 @@ int __compute_return_epc_for_insn(struct pt_regs *regs,
/* /*
* These are unconditional and in j_format. * These are unconditional and in j_format.
*/ */
case jalx_op:
case jal_op: case jal_op:
regs->regs[31] = regs->cp0_epc + 8; regs->regs[31] = regs->cp0_epc + 8;
case j_op: case j_op:
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment