Commit aa638cfe authored by Wei Li's avatar Wei Li Committed by Catalin Marinas

arm64: cpu_errata: Add Hisilicon TSV110 to spectre-v2 safe list

HiSilicon Taishan v110 CPUs didn't implement CSV2 field of the
ID_AA64PFR0_EL1, but spectre-v2 is mitigated by hardware, so
whitelist the MIDR in the safe list.
Signed-off-by: default avatarWei Li <liwei391@huawei.com>
[hanjun: re-write the commit log]
Signed-off-by: default avatarHanjun Guo <guohanjun@huawei.com>
Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent 8ae4bcf4
...@@ -547,6 +547,7 @@ static const struct midr_range spectre_v2_safe_list[] = { ...@@ -547,6 +547,7 @@ static const struct midr_range spectre_v2_safe_list[] = {
MIDR_ALL_VERSIONS(MIDR_CORTEX_A53), MIDR_ALL_VERSIONS(MIDR_CORTEX_A53),
MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53), MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53),
MIDR_ALL_VERSIONS(MIDR_HISI_TSV110),
{ /* sentinel */ } { /* sentinel */ }
}; };
......
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