Commit aa96e341 authored by Roel Kluin's avatar Roel Kluin Committed by Dave Airlie

drm/radeon: Fix setting of bits

Duplicate bits set
Signed-off-by: default avatarRoel Kluin <roel.kluin@gmail.com>
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
parent df748b02
...@@ -411,7 +411,7 @@ void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable) ...@@ -411,7 +411,7 @@ void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable)
R300_PIXCLK_TRANS_ALWAYS_ONb | R300_PIXCLK_TRANS_ALWAYS_ONb |
R300_PIXCLK_TVO_ALWAYS_ONb | R300_PIXCLK_TVO_ALWAYS_ONb |
R300_P2G2CLK_ALWAYS_ONb | R300_P2G2CLK_ALWAYS_ONb |
R300_P2G2CLK_ALWAYS_ONb); R300_P2G2CLK_DAC_ALWAYS_ONb);
WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
} else if (rdev->family >= CHIP_RV350) { } else if (rdev->family >= CHIP_RV350) {
tmp = RREG32_PLL(R300_SCLK_CNTL2); tmp = RREG32_PLL(R300_SCLK_CNTL2);
...@@ -464,7 +464,7 @@ void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable) ...@@ -464,7 +464,7 @@ void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable)
R300_PIXCLK_TRANS_ALWAYS_ONb | R300_PIXCLK_TRANS_ALWAYS_ONb |
R300_PIXCLK_TVO_ALWAYS_ONb | R300_PIXCLK_TVO_ALWAYS_ONb |
R300_P2G2CLK_ALWAYS_ONb | R300_P2G2CLK_ALWAYS_ONb |
R300_P2G2CLK_ALWAYS_ONb); R300_P2G2CLK_DAC_ALWAYS_ONb);
WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
tmp = RREG32_PLL(RADEON_MCLK_MISC); tmp = RREG32_PLL(RADEON_MCLK_MISC);
...@@ -654,7 +654,7 @@ void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable) ...@@ -654,7 +654,7 @@ void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable)
R300_PIXCLK_TRANS_ALWAYS_ONb | R300_PIXCLK_TRANS_ALWAYS_ONb |
R300_PIXCLK_TVO_ALWAYS_ONb | R300_PIXCLK_TVO_ALWAYS_ONb |
R300_P2G2CLK_ALWAYS_ONb | R300_P2G2CLK_ALWAYS_ONb |
R300_P2G2CLK_ALWAYS_ONb | R300_P2G2CLK_DAC_ALWAYS_ONb |
R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF); R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF);
WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
} else if (rdev->family >= CHIP_RV350) { } else if (rdev->family >= CHIP_RV350) {
...@@ -705,7 +705,7 @@ void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable) ...@@ -705,7 +705,7 @@ void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable)
R300_PIXCLK_TRANS_ALWAYS_ONb | R300_PIXCLK_TRANS_ALWAYS_ONb |
R300_PIXCLK_TVO_ALWAYS_ONb | R300_PIXCLK_TVO_ALWAYS_ONb |
R300_P2G2CLK_ALWAYS_ONb | R300_P2G2CLK_ALWAYS_ONb |
R300_P2G2CLK_ALWAYS_ONb | R300_P2G2CLK_DAC_ALWAYS_ONb |
R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF); R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF);
WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
} else { } else {
......
...@@ -881,7 +881,7 @@ static void radeon_legacy_tv_dac_mode_set(struct drm_encoder *encoder, ...@@ -881,7 +881,7 @@ static void radeon_legacy_tv_dac_mode_set(struct drm_encoder *encoder,
R420_TV_DAC_DACADJ_MASK | R420_TV_DAC_DACADJ_MASK |
R420_TV_DAC_RDACPD | R420_TV_DAC_RDACPD |
R420_TV_DAC_GDACPD | R420_TV_DAC_GDACPD |
R420_TV_DAC_GDACPD | R420_TV_DAC_BDACPD |
R420_TV_DAC_TVENABLE); R420_TV_DAC_TVENABLE);
} else { } else {
tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK | tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK |
...@@ -889,7 +889,7 @@ static void radeon_legacy_tv_dac_mode_set(struct drm_encoder *encoder, ...@@ -889,7 +889,7 @@ static void radeon_legacy_tv_dac_mode_set(struct drm_encoder *encoder,
RADEON_TV_DAC_DACADJ_MASK | RADEON_TV_DAC_DACADJ_MASK |
RADEON_TV_DAC_RDACPD | RADEON_TV_DAC_RDACPD |
RADEON_TV_DAC_GDACPD | RADEON_TV_DAC_GDACPD |
RADEON_TV_DAC_GDACPD); RADEON_TV_DAC_BDACPD);
} }
/* FIXME TV */ /* FIXME TV */
......
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