Commit aaca50ef authored by Ville Syrjälä's avatar Ville Syrjälä

drm/i915: Extend icl_sanitize_encoder_pll_mapping() to all DDI platforms

Now that all the encoder clock stuff is uniformly abstracted
for all hsw+ platforms, let's extend icl_sanitize_encoder_pll_mapping()
to cover all of them.

Not sure there is a particular benefit in doing so, but less special
cases always makes me happy.
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210224144214.24803-7-ville.syrjala@linux.intel.comReviewed-by: default avatarMika Kahola <mika.kahola@intel.com>
parent 0fbd8694
...@@ -2133,7 +2133,7 @@ static void intel_ddi_disable_clock(struct intel_encoder *encoder) ...@@ -2133,7 +2133,7 @@ static void intel_ddi_disable_clock(struct intel_encoder *encoder)
encoder->disable_clock(encoder); encoder->disable_clock(encoder);
} }
void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
{ {
struct drm_i915_private *i915 = to_i915(encoder->base.dev); struct drm_i915_private *i915 = to_i915(encoder->base.dev);
u32 port_mask; u32 port_mask;
......
...@@ -66,6 +66,6 @@ u32 ddi_signal_levels(struct intel_dp *intel_dp, ...@@ -66,6 +66,6 @@ u32 ddi_signal_levels(struct intel_dp *intel_dp,
int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder, int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder,
enum transcoder cpu_transcoder, enum transcoder cpu_transcoder,
bool enable, u32 hdcp_mask); bool enable, u32 hdcp_mask);
void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder); void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder);
#endif /* __INTEL_DDI_H__ */ #endif /* __INTEL_DDI_H__ */
...@@ -13146,8 +13146,8 @@ static void intel_sanitize_encoder(struct intel_encoder *encoder) ...@@ -13146,8 +13146,8 @@ static void intel_sanitize_encoder(struct intel_encoder *encoder)
/* notify opregion of the sanitized encoder state */ /* notify opregion of the sanitized encoder state */
intel_opregion_notify_encoder(encoder, connector && has_active_crtc); intel_opregion_notify_encoder(encoder, connector && has_active_crtc);
if (INTEL_GEN(dev_priv) >= 11) if (HAS_DDI(dev_priv))
icl_sanitize_encoder_pll_mapping(encoder); intel_ddi_sanitize_encoder_pll_mapping(encoder);
} }
/* FIXME read out full plane state for all planes */ /* FIXME read out full plane state for all planes */
......
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