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Commit aad36cd3 authored by Jakub Kicinski's avatar Jakub Kicinski
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Revert "Merge branch 'mv88e6xxx-dsa-bindings'" 

This reverts the following commits:

commit 53313ed2 ("dt-bindings: marvell: Add Marvell MV88E6060 DSA schema")
commit 0f35369b ("dt-bindings: marvell: Rewrite MV88E6xxx in schema")
commit 605a5f5d ("ARM64: dts: marvell: Fix some common switch mistakes")
commit bfedd842 ("ARM: dts: nxp: Fix some common switch mistakes")
commit 2b83557a ("ARM: dts: marvell: Fix some common switch mistakes")
commit ddae07ce ("dt-bindings: net: mvusb: Fix up DSA example")
commit b5ef6171 ("dt-bindings: net: dsa: Require ports or ethernet-ports")

As repoted by Vladimir, it breaks boot on the Turris MOX board.

Link: https://lore.kernel.org/all/20231025093632.fb2qdtunzaznd73z@skbuf/Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
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Documentation/devicetree/bindings/net/dsa/dsa.yaml
View file @ aad36cd3
......@@ -46,10 +46,4 @@ $defs:
$ref: dsa-port.yaml#
unevaluatedProperties: false
oneOf:
- required:
- ports
- required:
- ethernet-ports
...
Documentation/devicetree/bindings/net/dsa/marvell,mv88e6060.yaml deleted 100644 → 0
View file @ d0110443
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/dsa/marvell,mv88e6060.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Marvell MV88E6060 DSA switch
maintainers:
- Andrew Lunn <andrew@lunn.ch>
description:
The Marvell MV88E6060 switch has been produced and sold by Marvell
since at least 2008. The switch has one pin ADDR4 that controls the
MDIO address of the switch to be 0x10 or 0x00, and on the MDIO bus
connected to the switch, the PHYs inside the switch appear as
independent devices on address 0x00-0x04 or 0x10-0x14, so in difference
from many other DSA switches this switch does not have an internal
MDIO bus for the PHY devices.
properties:
compatible:
const: marvell,mv88e6060
description:
The MV88E6060 is the oldest Marvell DSA switch product, and
as such a bit limited in features compared to later hardware.
reg:
maxItems: 1
reset-gpios:
description:
GPIO to be used to reset the whole device
maxItems: 1
allOf:
- $ref: dsa.yaml#/$defs/ethernet-ports
required:
- compatible
- reg
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethernet-switch@16 {
compatible = "marvell,mv88e6060";
reg = <16>;
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
ethernet-port@0 {
reg = <0>;
label = "lan1";
};
ethernet-port@1 {
reg = <1>;
label = "lan2";
};
ethernet-port@2 {
reg = <2>;
label = "lan3";
};
ethernet-port@3 {
reg = <3>;
label = "lan4";
};
ethernet-port@5 {
reg = <5>;
phy-mode = "rev-mii";
ethernet = <&ethc>;
fixed-link {
speed = <100>;
full-duplex;
};
};
};
};
};
Documentation/devicetree/bindings/net/dsa/marvell,mv88e6xxx.yaml deleted 100644 → 0
View file @ d0110443
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/dsa/marvell,mv88e6xxx.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Marvell MV88E6xxx DSA switch family
maintainers:
- Andrew Lunn <andrew@lunn.ch>
description:
The Marvell MV88E6xxx switch series has been produced and sold
by Marvell since at least 2008. The switch has a few compatibles which
just indicate the base address of the switch, then operating systems
can investigate switch ID registers to find out which actual version
of the switch it is dealing with.
properties:
compatible:
enum:
- marvell,mv88e6085
- marvell,mv88e6190
- marvell,mv88e6250
description: |
marvell,mv88e6085: This switch uses base address 0x10.
This switch and its siblings will be autodetected from
ID registers found in the switch, so only "marvell,mv88e6085" should be
specified. This includes the following list of MV88Exxxx switches:
6085, 6095, 6097, 6123, 6131, 6141, 6161, 6165, 6171, 6172, 6175, 6176,
6185, 6240, 6320, 6321, 6341, 6350, 6351, 6352
marvell,mv88e6190: This switch uses base address 0x00.
This switch and its siblings will be autodetected from
ID registers found in the switch, so only "marvell,mv88e6190" should be
specified. This includes the following list of MV88Exxxx switches:
6190, 6190X, 6191, 6290, 6361, 6390, 6390X
marvell,mv88e6250: This switch uses base address 0x08 or 0x18.
This switch and its siblings will be autodetected from
ID registers found in the switch, so only "marvell,mv88e6250" should be
specified. This includes the following list of MV88Exxxx switches:
6220, 6250
reg:
maxItems: 1
eeprom-length:
$ref: /schemas/types.yaml#/definitions/uint32
description: Set to the length of an EEPROM connected to the switch. Must be
set if the switch can not detect the presence and/or size of a connected
EEPROM, otherwise optional.
reset-gpios:
description:
GPIO to be used to reset the whole device
maxItems: 1
interrupts:
description: The switch provides an external interrupt line, but it is
not always used by target systems.
maxItems: 1
interrupt-controller:
description: The switch has an internal interrupt controller used by
the different sub-blocks.
'#interrupt-cells':
description: The internal interrupt controller only supports triggering
on active high level interrupts so the second cell must alway be set to
IRQ_TYPE_LEVEL_HIGH.
const: 2
mdio:
$ref: /schemas/net/mdio.yaml#
unevaluatedProperties: false
description: Marvell MV88E6xxx switches have an varying combination of
internal and external MDIO buses, in some cases a combined bus that
can be used both internally and externally. This node is for the
primary bus, used internally and sometimes also externally.
mdio-external:
$ref: /schemas/net/mdio.yaml#
unevaluatedProperties: false
description: Marvell MV88E6xxx switches that have a separate external
MDIO bus use this port to access external components on the MDIO bus.
properties:
compatible:
const: marvell,mv88e6xxx-mdio-external
required:
- compatible
allOf:
- $ref: dsa.yaml#/$defs/ethernet-ports
required:
- compatible
- reg
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethernet-switch@0 {
compatible = "marvell,mv88e6085";
reg = <0>;
reset-gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
sw_phy0: ethernet-phy@0 {
reg = <0x0>;
};
sw_phy1: ethernet-phy@1 {
reg = <0x1>;
};
sw_phy2: ethernet-phy@2 {
reg = <0x2>;
};
sw_phy3: ethernet-phy@3 {
reg = <0x3>;
};
};
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
ethernet-port@0 {
reg = <0>;
label = "lan4";
phy-handle = <&sw_phy0>;
phy-mode = "internal";
};
ethernet-port@1 {
reg = <1>;
label = "lan3";
phy-handle = <&sw_phy1>;
phy-mode = "internal";
};
ethernet-port@2 {
reg = <2>;
label = "lan2";
phy-handle = <&sw_phy2>;
phy-mode = "internal";
};
ethernet-port@3 {
reg = <3>;
label = "lan1";
phy-handle = <&sw_phy3>;
phy-mode = "internal";
};
ethernet-port@5 {
reg = <5>;
ethernet = <&fec>;
phy-mode = "rgmii-id";
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
};
};
- |
#include <dt-bindings/interrupt-controller/irq.h>
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethernet-switch@0 {
compatible = "marvell,mv88e6190";
#interrupt-cells = <2>;
interrupt-controller;
interrupt-parent = <&gpio1>;
interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
pinctrl-0 = <&switch_interrupt_pins>;
pinctrl-names = "default";
reg = <0>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
switch0phy1: ethernet-phy@1 {
reg = <0x1>;
};
switch0phy2: ethernet-phy@2 {
reg = <0x2>;
};
switch0phy3: ethernet-phy@3 {
reg = <0x3>;
};
switch0phy4: ethernet-phy@4 {
reg = <0x4>;
};
switch0phy5: ethernet-phy@5 {
reg = <0x5>;
};
switch0phy6: ethernet-phy@6 {
reg = <0x6>;
};
switch0phy7: ethernet-phy@7 {
reg = <0x7>;
};
switch0phy8: ethernet-phy@8 {
reg = <0x8>;
};
};
mdio-external {
compatible = "marvell,mv88e6xxx-mdio-external";
#address-cells = <1>;
#size-cells = <0>;
phy1: ethernet-phy@b {
reg = <0xb>;
compatible = "ethernet-phy-ieee802.3-c45";
};
phy2: ethernet-phy@c {
reg = <0xc>;
compatible = "ethernet-phy-ieee802.3-c45";
};
};
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
ethernet-port@0 {
ethernet = <&eth0>;
phy-mode = "rgmii";
reg = <0>;
fixed-link {
full-duplex;
pause;
speed = <1000>;
};
};
ethernet-port@1 {
label = "lan1";
phy-handle = <&switch0phy1>;
reg = <1>;
};
ethernet-port@2 {
label = "lan2";
phy-handle = <&switch0phy2>;
reg = <2>;
};
ethernet-port@3 {
label = "lan3";
phy-handle = <&switch0phy3>;
reg = <3>;
};
ethernet-port@4 {
label = "lan4";
phy-handle = <&switch0phy4>;
reg = <4>;
};
ethernet-port@5 {
label = "lan5";
phy-handle = <&switch0phy5>;
reg = <5>;
};
ethernet-port@6 {
label = "lan6";
phy-handle = <&switch0phy6>;
reg = <6>;
};
ethernet-port@7 {
label = "lan7";
phy-handle = <&switch0phy7>;
reg = <7>;
};
ethernet-port@8 {
label = "lan8";
phy-handle = <&switch0phy8>;
reg = <8>;
};
ethernet-port@9 {
/* 88X3310P external phy */
label = "lan9";
phy-handle = <&phy1>;
phy-mode = "xaui";
reg = <9>;
};
ethernet-port@a {
/* 88X3310P external phy */
label = "lan10";
phy-handle = <&phy2>;
phy-mode = "xaui";
reg = <0xa>;
};
};
};
};
Documentation/devicetree/bindings/net/dsa/marvell.txt 0 → 100644
View file @ aad36cd3
Marvell DSA Switch Device Tree Bindings
---------------------------------------
WARNING: This binding is currently unstable. Do not program it into a
FLASH never to be changed again. Once this binding is stable, this
warning will be removed.
If you need a stable binding, use the old dsa.txt binding.
Marvell Switches are MDIO devices. The following properties should be
placed as a child node of an mdio device.
The properties described here are those specific to Marvell devices.
Additional required and optional properties can be found in dsa.txt.
The compatibility string is used only to find an identification register,
which is at a different MDIO base address in different switch families.
- "marvell,mv88e6085" : Switch has base address 0x10. Use with models:
6085, 6095, 6097, 6123, 6131, 6141, 6161, 6165,
6171, 6172, 6175, 6176, 6185, 6240, 6320, 6321,
6341, 6350, 6351, 6352
- "marvell,mv88e6190" : Switch has base address 0x00. Use with models:
6190, 6190X, 6191, 6290, 6361, 6390, 6390X
- "marvell,mv88e6250" : Switch has base address 0x08 or 0x18. Use with model:
6220, 6250
Required properties:
- compatible : Should be one of "marvell,mv88e6085",
"marvell,mv88e6190" or "marvell,mv88e6250" as
indicated above
- reg : Address on the MII bus for the switch.
Optional properties:
- reset-gpios : Should be a gpio specifier for a reset line
- interrupts : Interrupt from the switch
- interrupt-controller : Indicates the switch is itself an interrupt
controller. This is used for the PHY interrupts.
#interrupt-cells = <2> : Controller uses two cells, number and flag
- eeprom-length : Set to the length of an EEPROM connected to the
switch. Must be set if the switch can not detect
the presence and/or size of a connected EEPROM,
otherwise optional.
- mdio : Container of PHY and devices on the switches MDIO
bus.
- mdio? : Container of PHYs and devices on the external MDIO
bus. The node must contains a compatible string of
"marvell,mv88e6xxx-mdio-external"
Example:
mdio {
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <&gpio0>;
interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
#interrupt-cells = <2>;
switch0: switch@0 {
compatible = "marvell,mv88e6085";
reg = <0>;
reset-gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
switch1phy0: switch1phy0@0 {
reg = <0>;
interrupt-parent = <&switch0>;
interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
};
};
};
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
interrupt-parent = <&gpio0>;
interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
#interrupt-cells = <2>;
switch0: switch@0 {
compatible = "marvell,mv88e6190";
reg = <0>;
reset-gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
switch1phy0: switch1phy0@0 {
reg = <0>;
interrupt-parent = <&switch0>;
interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
};
};
mdio1 {
compatible = "marvell,mv88e6xxx-mdio-external";
#address-cells = <1>;
#size-cells = <0>;
switch1phy9: switch1phy0@9 {
reg = <9>;
};
};
};
};
Documentation/devicetree/bindings/net/marvell,mvusb.yaml
View file @ aad36cd3
......@@ -50,14 +50,11 @@ examples:
#address-cells = <1>;
#size-cells = <0>;
ethernet-switch@0 {
switch@0 {
compatible = "marvell,mv88e6190";
reg = <0x0>;
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
ports {
/* Port definitions */
};
......
MAINTAINERS
View file @ aad36cd3
......@@ -12626,8 +12626,7 @@ MARVELL 88E6XXX ETHERNET SWITCH FABRIC DRIVER
M: Andrew Lunn <andrew@lunn.ch>
L: netdev@vger.kernel.org
S: Maintained
F: Documentation/devicetree/bindings/net/dsa/marvell,mv88e6060.yaml
F: Documentation/devicetree/bindings/net/dsa/marvell,mv88e6xxx.yaml
F: Documentation/devicetree/bindings/net/dsa/marvell.txt
F: Documentation/networking/devlink/mv88e6xxx.rst
F: drivers/net/dsa/mv88e6xxx/
F: include/linux/dsa/mv88e6xxx.h
......
arch/arm/boot/dts/marvell/armada-370-rd.dts
View file @ aad36cd3
......@@ -149,37 +149,39 @@ led@0 {
};
};
switch: ethernet-switch@10 {
switch: switch@10 {
compatible = "marvell,mv88e6085";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x10>;
interrupt-controller;
#interrupt-cells = <2>;
ethernet-ports {
ports {
#address-cells = <1>;
#size-cells = <0>;
ethernet-port@0 {
port@0 {
reg = <0>;
label = "lan0";
};
ethernet-port@1 {
port@1 {
reg = <1>;
label = "lan1";
};
ethernet-port@2 {
port@2 {
reg = <2>;
label = "lan2";
};
ethernet-port@3 {
port@3 {
reg = <3>;
label = "lan3";
};
ethernet-port@5 {
port@5 {
reg = <5>;
ethernet = <&eth1>;
phy-mode = "rgmii-id";
......@@ -194,25 +196,25 @@ mdio {
#address-cells = <1>;
#size-cells = <0>;
switchphy0: ethernet-phy@0 {
switchphy0: switchphy@0 {
reg = <0>;
interrupt-parent = <&switch>;
interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
};
switchphy1: ethernet-phy@1 {
switchphy1: switchphy@1 {
reg = <1>;
interrupt-parent = <&switch>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
};
switchphy2: ethernet-phy@2 {
switchphy2: switchphy@2 {
reg = <2>;
interrupt-parent = <&switch>;
interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
};
switchphy3: ethernet-phy@3 {
switchphy3: switchphy@3 {
reg = <3>;
interrupt-parent = <&switch>;
interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
......
arch/arm/boot/dts/marvell/armada-381-netgear-gs110emx.dts
View file @ aad36cd3
......@@ -77,49 +77,51 @@ &mdio {
pinctrl-0 = <&mdio_pins>;
status = "okay";
ethernet-switch@0 {
switch@0 {
compatible = "marvell,mv88e6190";
#address-cells = <1>;
#interrupt-cells = <2>;
interrupt-controller;
interrupt-parent = <&gpio1>;
interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
pinctrl-0 = <&switch_interrupt_pins>;
pinctrl-names = "default";
#size-cells = <0>;
reg = <0>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
switch0phy1: ethernet-phy@1 {
switch0phy1: switch0phy1@1 {
reg = <0x1>;
};
switch0phy2: ethernet-phy@2 {
switch0phy2: switch0phy2@2 {
reg = <0x2>;
};
switch0phy3: ethernet-phy@3 {
switch0phy3: switch0phy3@3 {
reg = <0x3>;
};
switch0phy4: ethernet-phy@4 {
switch0phy4: switch0phy4@4 {
reg = <0x4>;
};
switch0phy5: ethernet-phy@5 {
switch0phy5: switch0phy5@5 {
reg = <0x5>;
};
switch0phy6: ethernet-phy@6 {
switch0phy6: switch0phy6@6 {
reg = <0x6>;
};
switch0phy7: ethernet-phy@7 {
switch0phy7: switch0phy7@7 {
reg = <0x7>;
};
switch0phy8: ethernet-phy@8 {
switch0phy8: switch0phy8@8 {
reg = <0x8>;
};
};
......@@ -140,11 +142,11 @@ phy2: ethernet-phy@c {
};
};
ethernet-ports {
ports {
#address-cells = <1>;
#size-cells = <0>;
ethernet-port@0 {
port@0 {
ethernet = <&eth0>;
phy-mode = "rgmii";
reg = <0>;
......@@ -156,55 +158,55 @@ fixed-link {
};
};
ethernet-port@1 {
port@1 {
label = "lan1";
phy-handle = <&switch0phy1>;
reg = <1>;
};
ethernet-port@2 {
port@2 {
label = "lan2";
phy-handle = <&switch0phy2>;
reg = <2>;
};
ethernet-port@3 {
port@3 {
label = "lan3";
phy-handle = <&switch0phy3>;
reg = <3>;
};
ethernet-port@4 {
port@4 {
label = "lan4";
phy-handle = <&switch0phy4>;
reg = <4>;
};
ethernet-port@5 {
port@5 {
label = "lan5";
phy-handle = <&switch0phy5>;
reg = <5>;
};
ethernet-port@6 {
port@6 {
label = "lan6";
phy-handle = <&switch0phy6>;
reg = <6>;
};
ethernet-port@7 {
port@7 {
label = "lan7";
phy-handle = <&switch0phy7>;
reg = <7>;
};
ethernet-port@8 {
port@8 {
label = "lan8";
phy-handle = <&switch0phy8>;
reg = <8>;
};
ethernet-port@9 {
port@9 {
/* 88X3310P external phy */
label = "lan9";
phy-handle = <&phy1>;
......@@ -212,7 +214,7 @@ ethernet-port@9 {
reg = <9>;
};
ethernet-port@a {
port@a {
/* 88X3310P external phy */
label = "lan10";
phy-handle = <&phy2>;
......
arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-l8.dts
View file @ aad36cd3
......@@ -7,66 +7,66 @@ / {
};
&mdio {
switch0: ethernet-switch@4 {
switch0: switch0@4 {
compatible = "marvell,mv88e6190";
reg = <4>;
pinctrl-names = "default";
pinctrl-0 = <&cf_gtr_switch_reset_pins>;
reset-gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
ethernet-ports {
ports {
#address-cells = <1>;
#size-cells = <0>;
ethernet-port@1 {
port@1 {
reg = <1>;
label = "lan8";
phy-handle = <&switch0phy0>;
};
ethernet-port@2 {
port@2 {
reg = <2>;
label = "lan7";
phy-handle = <&switch0phy1>;
};
ethernet-port@3 {
port@3 {
reg = <3>;
label = "lan6";
phy-handle = <&switch0phy2>;
};
ethernet-port@4 {
port@4 {
reg = <4>;
label = "lan5";
phy-handle = <&switch0phy3>;
};
ethernet-port@5 {
port@5 {
reg = <5>;
label = "lan4";
phy-handle = <&switch0phy4>;
};
ethernet-port@6 {
port@6 {
reg = <6>;
label = "lan3";
phy-handle = <&switch0phy5>;
};
ethernet-port@7 {
port@7 {
reg = <7>;
label = "lan2";
phy-handle = <&switch0phy6>;
};
ethernet-port@8 {
port@8 {
reg = <8>;
label = "lan1";
phy-handle = <&switch0phy7>;
};
ethernet-port@10 {
port@10 {
reg = <10>;
phy-mode = "2500base-x";
......@@ -83,35 +83,35 @@ mdio {
#address-cells = <1>;
#size-cells = <0>;
switch0phy0: ethernet-phy@1 {
switch0phy0: switch0phy0@1 {
reg = <0x1>;
};
switch0phy1: ethernet-phy@2 {
switch0phy1: switch0phy1@2 {
reg = <0x2>;
};
switch0phy2: ethernet-phy@3 {
switch0phy2: switch0phy2@3 {
reg = <0x3>;
};
switch0phy3: ethernet-phy@4 {
switch0phy3: switch0phy3@4 {
reg = <0x4>;
};
switch0phy4: ethernet-phy@5 {
switch0phy4: switch0phy4@5 {
reg = <0x5>;
};
switch0phy5: ethernet-phy@6 {
switch0phy5: switch0phy5@6 {
reg = <0x6>;
};
switch0phy6: ethernet-phy@7 {
switch0phy6: switch0phy6@7 {
reg = <0x7>;
};
switch0phy7: ethernet-phy@8 {
switch0phy7: switch0phy7@8 {
reg = <0x8>;
};
};
......
arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-s4.dts
View file @ aad36cd3
......@@ -11,42 +11,42 @@ &sfp0 {
};
&mdio {
switch0: ethernet-switch@4 {
switch0: switch0@4 {
compatible = "marvell,mv88e6085";
reg = <4>;
pinctrl-names = "default";
pinctrl-0 = <&cf_gtr_switch_reset_pins>;
reset-gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
ethernet-ports {
ports {
#address-cells = <1>;
#size-cells = <0>;
ethernet-port@1 {
port@1 {
reg = <1>;
label = "lan2";
phy-handle = <&switch0phy0>;
};
ethernet-port@2 {
port@2 {
reg = <2>;
label = "lan1";
phy-handle = <&switch0phy1>;
};
ethernet-port@3 {
port@3 {
reg = <3>;
label = "lan4";
phy-handle = <&switch0phy2>;
};
ethernet-port@4 {
port@4 {
reg = <4>;
label = "lan3";
phy-handle = <&switch0phy3>;
};
ethernet-port@5 {
port@5 {
reg = <5>;
phy-mode = "2500base-x";
ethernet = <&eth1>;
......@@ -63,19 +63,19 @@ mdio {
#address-cells = <1>;
#size-cells = <0>;
switch0phy0: ethernet-phy@11 {
switch0phy0: switch0phy0@11 {
reg = <0x11>;
};
switch0phy1: ethernet-phy@12 {
switch0phy1: switch0phy1@12 {
reg = <0x12>;
};
switch0phy2: ethernet-phy@13 {
switch0phy2: switch0phy2@13 {
reg = <0x13>;
};
switch0phy3: ethernet-phy@14 {
switch0phy3: switch0phy3@14 {
reg = <0x14>;
};
};
......
arch/arm/boot/dts/marvell/armada-385-linksys.dtsi
View file @ aad36cd3
......@@ -158,40 +158,42 @@ nand: nand@0 {
&mdio {
status = "okay";
ethernet-switch@0 {
switch@0 {
compatible = "marvell,mv88e6085";
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
ethernet-ports {
ports {
#address-cells = <1>;
#size-cells = <0>;
ethernet-port@0 {
port@0 {
reg = <0>;
label = "lan4";
};
ethernet-port@1 {
port@1 {
reg = <1>;
label = "lan3";
};
ethernet-port@2 {
port@2 {
reg = <2>;
label = "lan2";
};
ethernet-port@3 {
port@3 {
reg = <3>;
label = "lan1";
};
ethernet-port@4 {
port@4 {
reg = <4>;
label = "wan";
};
ethernet-port@5 {
port@5 {
reg = <5>;
phy-mode = "sgmii";
ethernet = <&eth2>;
......
arch/arm/boot/dts/marvell/armada-385-turris-omnia.dts
View file @ aad36cd3
......@@ -435,10 +435,12 @@ phy1: ethernet-phy@1 {
};
/* Switch MV88E6176 at address 0x10 */
ethernet-switch@10 {
switch@10 {
pinctrl-names = "default";
pinctrl-0 = <&swint_pins>;
compatible = "marvell,mv88e6085";
#address-cells = <1>;
#size-cells = <0>;
dsa,member = <0 0>;
reg = <0x10>;
......@@ -446,36 +448,36 @@ ethernet-switch@10 {
interrupt-parent = <&gpio1>;
interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
ethernet-ports {
ports {
#address-cells = <1>;
#size-cells = <0>;
ethernet-port@0 {
ports@0 {
reg = <0>;
label = "lan0";
};
ethernet-port@1 {
ports@1 {
reg = <1>;
label = "lan1";
};
ethernet-port@2 {
ports@2 {
reg = <2>;
label = "lan2";
};
ethernet-port@3 {
ports@3 {
reg = <3>;
label = "lan3";
};
ethernet-port@4 {
ports@4 {
reg = <4>;
label = "lan4";
};
ethernet-port@5 {
ports@5 {
reg = <5>;
ethernet = <&eth1>;
phy-mode = "rgmii-id";
......@@ -486,7 +488,7 @@ fixed-link {
};
};
ethernet-port@6 {
ports@6 {
reg = <6>;
ethernet = <&eth0>;
phy-mode = "rgmii-id";
......
arch/arm/boot/dts/marvell/armada-388-clearfog.dts
View file @ aad36cd3
......@@ -92,42 +92,44 @@ pcie2-0-w-disable-hog {
&mdio {
status = "okay";
ethernet-switch@4 {
switch@4 {
compatible = "marvell,mv88e6085";
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
pinctrl-0 = <&clearfog_dsa0_clk_pins &clearfog_dsa0_pins>;
pinctrl-names = "default";
ethernet-ports {
ports {
#address-cells = <1>;
#size-cells = <0>;
ethernet-port@0 {
port@0 {
reg = <0>;
label = "lan5";
};
ethernet-port@1 {
port@1 {
reg = <1>;
label = "lan4";
};
ethernet-port@2 {
port@2 {
reg = <2>;
label = "lan3";
};
ethernet-port@3 {
port@3 {
reg = <3>;
label = "lan2";
};
ethernet-port@4 {
port@4 {
reg = <4>;
label = "lan1";
};
ethernet-port@5 {
port@5 {
reg = <5>;
ethernet = <&eth1>;
phy-mode = "1000base-x";
......@@ -138,7 +140,7 @@ fixed-link {
};
};
ethernet-port@6 {
port@6 {
/* 88E1512 external phy */
reg = <6>;
label = "lan6";
......
arch/arm/boot/dts/marvell/armada-xp-linksys-mamba.dts
View file @ aad36cd3
......@@ -265,40 +265,42 @@ flash@0 {
&mdio {
status = "okay";
ethernet-switch@0 {
switch@0 {
compatible = "marvell,mv88e6085";
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
ethernet-ports {
ports {
#address-cells = <1>;
#size-cells = <0>;
ethernet-port@0 {
port@0 {
reg = <0>;
label = "lan4";
};
ethernet-port@1 {
port@1 {
reg = <1>;
label = "lan3";
};
ethernet-port@2 {
port@2 {
reg = <2>;
label = "lan2";
};
ethernet-port@3 {
port@3 {
reg = <3>;
label = "lan1";
};
ethernet-port@4 {
port@4 {
reg = <4>;
label = "internet";
};
ethernet-port@5 {
port@5 {
reg = <5>;
phy-mode = "rgmii-id";
ethernet = <&eth0>;
......
arch/arm/boot/dts/nxp/vf/vf610-zii-cfu1.dts
View file @ aad36cd3
......@@ -162,7 +162,7 @@ mdio1: mdio {
suppress-preamble;
status = "okay";
switch0: ethernet-switch@0 {
switch0: switch0@0 {
compatible = "marvell,mv88e6085";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_switch>;
......@@ -173,26 +173,26 @@ switch0: ethernet-switch@0 {
interrupt-controller;
#interrupt-cells = <2>;
ethernet-ports {
ports {
#address-cells = <1>;
#size-cells = <0>;
ethernet-port@0 {
port@0 {
reg = <0>;
label = "eth_cu_1000_1";
};
ethernet-port@1 {
port@1 {
reg = <1>;
label = "eth_cu_1000_2";
};
ethernet-port@2 {
port@2 {
reg = <2>;
label = "eth_cu_1000_3";
};
ethernet-port@5 {
port@5 {
reg = <5>;
label = "eth_fc_1000_1";
phy-mode = "1000base-x";
......@@ -200,7 +200,7 @@ ethernet-port@5 {
sfp = <&sff>;
};
ethernet-port@6 {
port@6 {
reg = <6>;
phy-mode = "rmii";
ethernet = <&fec1>;
......
arch/arm/boot/dts/nxp/vf/vf610-zii-scu4-aib.dts
View file @ aad36cd3
......@@ -47,17 +47,17 @@ mdio_mux_1: mdio@1 {
#address-cells = <1>;
#size-cells = <0>;
switch0: ethernet-switch@0 {
switch0: switch0@0 {
compatible = "marvell,mv88e6190";
reg = <0>;
dsa,member = <0 0>;
eeprom-length = <65536>;
ethernet-ports {
ports {
#address-cells = <1>;
#size-cells = <0>;
ethernet-port@0 {
port@0 {
reg = <0>;
phy-mode = "rmii";
ethernet = <&fec1>;
......@@ -68,37 +68,37 @@ fixed-link {
};
};
ethernet-port@1 {
port@1 {
reg = <1>;
label = "aib2main_1";
};
ethernet-port@2 {
port@2 {
reg = <2>;
label = "aib2main_2";
};
ethernet-port@3 {
port@3 {
reg = <3>;
label = "eth_cu_1000_5";
};
ethernet-port@4 {
port@4 {
reg = <4>;
label = "eth_cu_1000_6";
};
ethernet-port@5 {
port@5 {
reg = <5>;
label = "eth_cu_1000_4";
};
ethernet-port@6 {
port@6 {
reg = <6>;
label = "eth_cu_1000_7";
};
ethernet-port@7 {
port@7 {
reg = <7>;
label = "modem_pic";
......@@ -108,7 +108,7 @@ fixed-link {
};
};
switch0port10: ethernet-port@10 {
switch0port10: port@10 {
reg = <10>;
label = "dsa";
phy-mode = "xgmii";
......@@ -130,32 +130,32 @@ mdio_mux_2: mdio@2 {
#address-cells = <1>;
#size-cells = <0>;
switch1: ethernet-switch@0 {
switch1: switch1@0 {
compatible = "marvell,mv88e6190";
reg = <0>;
dsa,member = <0 1>;
eeprom-length = <65536>;
ethernet-ports {
ports {
#address-cells = <1>;
#size-cells = <0>;
ethernet-port@1 {
port@1 {
reg = <1>;
label = "eth_cu_1000_3";
};
ethernet-port@2 {
port@2 {
reg = <2>;
label = "eth_cu_100_2";
};
ethernet-port@3 {
port@3 {
reg = <3>;
label = "eth_cu_100_3";
};
switch1port9: ethernet-port@9 {
switch1port9: port@9 {
reg = <9>;
label = "dsa";
phy-mode = "xgmii";
......@@ -168,7 +168,7 @@ fixed-link {
};
};
switch1port10: ethernet-port@10 {
switch1port10: port@10 {
reg = <10>;
label = "dsa";
phy-mode = "xgmii";
......@@ -188,17 +188,17 @@ mdio_mux_4: mdio@4 {
#address-cells = <1>;
#size-cells = <0>;
switch2: ethernet-switch@0 {
switch2: switch2@0 {
compatible = "marvell,mv88e6190";
reg = <0>;
dsa,member = <0 2>;
eeprom-length = <65536>;
ethernet-ports {
ports {
#address-cells = <1>;
#size-cells = <0>;
ethernet-port@2 {
port@2 {
reg = <2>;
label = "eth_fc_1000_2";
phy-mode = "1000base-x";
......@@ -206,7 +206,7 @@ ethernet-port@2 {
sfp = <&sff1>;
};
ethernet-port@3 {
port@3 {
reg = <3>;
label = "eth_fc_1000_3";
phy-mode = "1000base-x";
......@@ -214,7 +214,7 @@ ethernet-port@3 {
sfp = <&sff2>;
};
ethernet-port@4 {
port@4 {
reg = <4>;
label = "eth_fc_1000_4";
phy-mode = "1000base-x";
......@@ -222,7 +222,7 @@ ethernet-port@4 {
sfp = <&sff3>;
};
ethernet-port@5 {
port@5 {
reg = <5>;
label = "eth_fc_1000_5";
phy-mode = "1000base-x";
......@@ -230,7 +230,7 @@ ethernet-port@5 {
sfp = <&sff4>;
};
ethernet-port@6 {
port@6 {
reg = <6>;
label = "eth_fc_1000_6";
phy-mode = "1000base-x";
......@@ -238,7 +238,7 @@ ethernet-port@6 {
sfp = <&sff5>;
};
ethernet-port@7 {
port@7 {
reg = <7>;
label = "eth_fc_1000_7";
phy-mode = "1000base-x";
......@@ -246,7 +246,7 @@ ethernet-port@7 {
sfp = <&sff6>;
};
ethernet-port@9 {
port@9 {
reg = <9>;
label = "eth_fc_1000_1";
phy-mode = "1000base-x";
......@@ -254,7 +254,7 @@ ethernet-port@9 {
sfp = <&sff0>;
};
switch2port10: ethernet-port@10 {
switch2port10: port@10 {
reg = <10>;
label = "dsa";
phy-mode = "2500base-x";
......@@ -276,17 +276,17 @@ mdio_mux_8: mdio@8 {
#address-cells = <1>;
#size-cells = <0>;
switch3: ethernet-switch@0 {
switch3: switch3@0 {
compatible = "marvell,mv88e6190";
reg = <0>;
dsa,member = <0 3>;
eeprom-length = <65536>;
ethernet-ports {
ports {
#address-cells = <1>;
#size-cells = <0>;
ethernet-port@2 {
port@2 {
reg = <2>;
label = "eth_fc_1000_8";
phy-mode = "1000base-x";
......@@ -294,7 +294,7 @@ ethernet-port@2 {
sfp = <&sff7>;
};
ethernet-port@3 {
port@3 {
reg = <3>;
label = "eth_fc_1000_9";
phy-mode = "1000base-x";
......@@ -302,7 +302,7 @@ ethernet-port@3 {
sfp = <&sff8>;
};
ethernet-port@4 {
port@4 {
reg = <4>;
label = "eth_fc_1000_10";
phy-mode = "1000base-x";
......@@ -310,7 +310,7 @@ ethernet-port@4 {
sfp = <&sff9>;
};
switch3port9: ethernet-port@9 {
switch3port9: port@9 {
reg = <9>;
label = "dsa";
phy-mode = "2500base-x";
......@@ -322,7 +322,7 @@ fixed-link {
};
};
switch3port10: ethernet-port@10 {
switch3port10: port@10 {
reg = <10>;
label = "dsa";
phy-mode = "xgmii";
......
arch/arm/boot/dts/nxp/vf/vf610-zii-spb4.dts
View file @ aad36cd3
......@@ -123,7 +123,7 @@ mdio1: mdio {
suppress-preamble;
status = "okay";
switch0: ethernet-switch@0 {
switch0: switch0@0 {
compatible = "marvell,mv88e6190";
pinctrl-0 = <&pinctrl_gpio_switch0>;
pinctrl-names = "default";
......@@ -134,11 +134,11 @@ switch0: ethernet-switch@0 {
interrupt-controller;
#interrupt-cells = <2>;
ethernet-ports {
ports {
#address-cells = <1>;
#size-cells = <0>;
ethernet-port@0 {
port@0 {
reg = <0>;
phy-mode = "rmii";
ethernet = <&fec1>;
......@@ -149,32 +149,32 @@ fixed-link {
};
};
ethernet-port@1 {
port@1 {
reg = <1>;
label = "eth_cu_1000_1";
};
ethernet-port@2 {
port@2 {
reg = <2>;
label = "eth_cu_1000_2";
};
ethernet-port@3 {
port@3 {
reg = <3>;
label = "eth_cu_1000_3";
};
ethernet-port@4 {
port@4 {
reg = <4>;
label = "eth_cu_1000_4";
};
ethernet-port@5 {
port@5 {
reg = <5>;
label = "eth_cu_1000_5";
};
ethernet-port@6 {
port@6 {
reg = <6>;
label = "eth_cu_1000_6";
};
......
arch/arm/boot/dts/nxp/vf/vf610-zii-ssmb-dtu.dts
View file @ aad36cd3
......@@ -112,7 +112,7 @@ mdio1: mdio {
suppress-preamble;
status = "okay";
switch0: ethernet-switch@0 {
switch0: switch0@0 {
compatible = "marvell,mv88e6190";
pinctrl-0 = <&pinctrl_gpio_switch0>;
pinctrl-names = "default";
......@@ -123,11 +123,11 @@ switch0: ethernet-switch@0 {
interrupt-controller;
#interrupt-cells = <2>;
ethernet-ports {
ports {
#address-cells = <1>;
#size-cells = <0>;
ethernet-port@0 {
port@0 {
reg = <0>;
phy-mode = "rmii";
ethernet = <&fec1>;
......@@ -138,27 +138,27 @@ fixed-link {
};
};
ethernet-port@1 {
port@1 {
reg = <1>;
label = "eth_cu_100_3";
};
ethernet-port@5 {
port@5 {
reg = <5>;
label = "eth_cu_1000_4";
};
ethernet-port@6 {
port@6 {
reg = <6>;
label = "eth_cu_1000_5";
};
ethernet-port@8 {
port@8 {
reg = <8>;
label = "eth_cu_1000_1";
};
ethernet-port@9 {
port@9 {
reg = <9>;
label = "eth_cu_1000_2";
phy-handle = <&phy9>;
......@@ -167,12 +167,12 @@ ethernet-port@9 {
};
};
mdio-external {
mdio1 {
compatible = "marvell,mv88e6xxx-mdio-external";
#address-cells = <1>;
#size-cells = <0>;
phy9: ethernet-phy@0 {
phy9: phy9@0 {
compatible = "ethernet-phy-ieee802.3-c45";
pinctrl-0 = <&pinctrl_gpio_phy9>;
pinctrl-names = "default";
......
arch/arm/boot/dts/nxp/vf/vf610-zii-ssmb-spu3.dts
View file @ aad36cd3
......@@ -137,7 +137,7 @@ mdio1: mdio {
suppress-preamble;
status = "okay";
switch0: ethernet-switch@0 {
switch0: switch0@0 {
compatible = "marvell,mv88e6190";
pinctrl-0 = <&pinctrl_gpio_switch0>;
pinctrl-names = "default";
......@@ -148,11 +148,11 @@ switch0: ethernet-switch@0 {
interrupt-controller;
#interrupt-cells = <2>;
ethernet-ports {
ports {
#address-cells = <1>;
#size-cells = <0>;
ethernet-port@0 {
port@0 {
reg = <0>;
phy-mode = "rmii";
ethernet = <&fec1>;
......@@ -163,32 +163,32 @@ fixed-link {
};
};
ethernet-port@1 {
port@1 {
reg = <1>;
label = "eth_cu_1000_1";
};
ethernet-port@2 {
port@2 {
reg = <2>;
label = "eth_cu_1000_2";
};
ethernet-port@3 {
port@3 {
reg = <3>;
label = "eth_cu_1000_3";
};
ethernet-port@4 {
port@4 {
reg = <4>;
label = "eth_cu_1000_4";
};
ethernet-port@5 {
port@5 {
reg = <5>;
label = "eth_cu_1000_5";
};
ethernet-port@6 {
port@6 {
reg = <6>;
label = "eth_cu_1000_6";
};
......
arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts
View file @ aad36cd3
......@@ -126,32 +126,32 @@ &switch0 {
reset-gpios = <&gpiosb 23 GPIO_ACTIVE_LOW>;
ethernet-ports {
switch0port1: ethernet-port@1 {
ports {
switch0port1: port@1 {
reg = <1>;
label = "lan0";
phy-handle = <&switch0phy0>;
};
switch0port2: ethernet-port@2 {
switch0port2: port@2 {
reg = <2>;
label = "lan1";
phy-handle = <&switch0phy1>;
};
switch0port3: ethernet-port@3 {
switch0port3: port@3 {
reg = <3>;
label = "lan2";
phy-handle = <&switch0phy2>;
};
switch0port4: ethernet-port@4 {
switch0port4: port@4 {
reg = <4>;
label = "lan3";
phy-handle = <&switch0phy3>;
};
switch0port5: ethernet-port@5 {
switch0port5: port@5 {
reg = <5>;
label = "wan";
phy-handle = <&extphy>;
......@@ -160,7 +160,7 @@ switch0port5: ethernet-port@5 {
};
mdio {
switch0phy3: ethernet-phy@14 {
switch0phy3: switch0phy3@14 {
reg = <0x14>;
};
};
......
arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi
View file @ aad36cd3
......@@ -145,17 +145,19 @@ &usb2 {
};
&mdio {
switch0: ethernet-switch@1 {
switch0: switch0@1 {
compatible = "marvell,mv88e6085";
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
dsa,member = <0 0>;
ethernet-ports {
ports {
#address-cells = <1>;
#size-cells = <0>;
switch0port0: ethernet-port@0 {
switch0port0: port@0 {
reg = <0>;
label = "cpu";
ethernet = <&eth0>;
......@@ -166,19 +168,19 @@ fixed-link {
};
};
switch0port1: ethernet-port@1 {
switch0port1: port@1 {
reg = <1>;
label = "wan";
phy-handle = <&switch0phy0>;
};
switch0port2: ethernet-port@2 {
switch0port2: port@2 {
reg = <2>;
label = "lan0";
phy-handle = <&switch0phy1>;
};
switch0port3: ethernet-port@3 {
switch0port3: port@3 {
reg = <3>;
label = "lan1";
phy-handle = <&switch0phy2>;
......@@ -190,13 +192,13 @@ mdio {
#address-cells = <1>;
#size-cells = <0>;
switch0phy0: ethernet-phy@11 {
switch0phy0: switch0phy0@11 {
reg = <0x11>;
};
switch0phy1: ethernet-phy@12 {
switch0phy1: switch0phy1@12 {
reg = <0x12>;
};
switch0phy2: ethernet-phy@13 {
switch0phy2: switch0phy2@13 {
reg = <0x13>;
};
};
......
arch/arm64/boot/dts/marvell/armada-3720-gl-mv1000.dts
View file @ aad36cd3
......@@ -152,29 +152,31 @@ &uart0 {
};
&mdio {
switch0: ethernet-switch@1 {
switch0: switch0@1 {
compatible = "marvell,mv88e6085";
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
dsa,member = <0 0>;
ports: ethernet-ports {
ports: ports {
#address-cells = <1>;
#size-cells = <0>;
ethernet-port@0 {
port@0 {
reg = <0>;
label = "cpu";
ethernet = <&eth0>;
};
ethernet-port@1 {
port@1 {
reg = <1>;
label = "wan";
phy-handle = <&switch0phy0>;
};
ethernet-port@2 {
port@2 {
reg = <2>;
label = "lan0";
phy-handle = <&switch0phy1>;
......@@ -183,7 +185,7 @@ ethernet-port@2 {
nvmem-cell-names = "mac-address";
};
ethernet-port@3 {
port@3 {
reg = <3>;
label = "lan1";
phy-handle = <&switch0phy2>;
......@@ -197,13 +199,13 @@ mdio {
#address-cells = <1>;
#size-cells = <0>;
switch0phy0: ethernet-phy@11 {
switch0phy0: switch0phy0@11 {
reg = <0x11>;
};
switch0phy1: ethernet-phy@12 {
switch0phy1: switch0phy1@12 {
reg = <0x12>;
};
switch0phy2: ethernet-phy@13 {
switch0phy2: switch0phy2@13 {
reg = <0x13>;
};
};
......
arch/arm64/boot/dts/marvell/armada-7040-mochabin.dts
View file @ aad36cd3
......@@ -301,8 +301,10 @@ eth2phy: ethernet-phy@1 {
};
/* 88E6141 Topaz switch */
switch: ethernet-switch@3 {
switch: switch@3 {
compatible = "marvell,mv88e6085";
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
pinctrl-names = "default";
......@@ -312,35 +314,35 @@ switch: ethernet-switch@3 {
interrupt-parent = <&cp0_gpio1>;
interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
ethernet-ports {
ports {
#address-cells = <1>;
#size-cells = <0>;
swport1: ethernet-port@1 {
swport1: port@1 {
reg = <1>;
label = "lan0";
phy-handle = <&swphy1>;
};
swport2: ethernet-port@2 {
swport2: port@2 {
reg = <2>;
label = "lan1";
phy-handle = <&swphy2>;
};
swport3: ethernet-port@3 {
swport3: port@3 {
reg = <3>;
label = "lan2";
phy-handle = <&swphy3>;
};
swport4: ethernet-port@4 {
swport4: port@4 {
reg = <4>;
label = "lan3";
phy-handle = <&swphy4>;
};
ethernet-port@5 {
port@5 {
reg = <5>;
label = "cpu";
ethernet = <&cp0_eth1>;
......@@ -353,19 +355,19 @@ mdio {
#address-cells = <1>;
#size-cells = <0>;
swphy1: ethernet-phy@17 {
swphy1: swphy1@17 {
reg = <17>;
};
swphy2: ethernet-phy@18 {
swphy2: swphy2@18 {
reg = <18>;
};
swphy3: ethernet-phy@19 {
swphy3: swphy3@19 {
reg = <19>;
};
swphy4: ethernet-phy@20 {
swphy4: swphy4@20 {
reg = <20>;
};
};
......
arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts
View file @ aad36cd3
......@@ -497,42 +497,42 @@ ge_phy: ethernet-phy@0 {
reset-deassert-us = <10000>;
};
switch0: ethernet-switch@4 {
switch0: switch0@4 {
compatible = "marvell,mv88e6085";
reg = <4>;
pinctrl-names = "default";
pinctrl-0 = <&cp1_switch_reset_pins>;
reset-gpios = <&cp1_gpio1 24 GPIO_ACTIVE_LOW>;
ethernet-ports {
ports {
#address-cells = <1>;
#size-cells = <0>;
ethernet-port@1 {
port@1 {
reg = <1>;
label = "lan2";
phy-handle = <&switch0phy0>;
};
ethernet-port@2 {
port@2 {
reg = <2>;
label = "lan1";
phy-handle = <&switch0phy1>;
};
ethernet-port@3 {
port@3 {
reg = <3>;
label = "lan4";
phy-handle = <&switch0phy2>;
};
ethernet-port@4 {
port@4 {
reg = <4>;
label = "lan3";
phy-handle = <&switch0phy3>;
};
ethernet-port@5 {
port@5 {
reg = <5>;
label = "cpu";
ethernet = <&cp1_eth2>;
......@@ -545,19 +545,19 @@ mdio {
#address-cells = <1>;
#size-cells = <0>;
switch0phy0: ethernet-phy@11 {
switch0phy0: switch0phy0@11 {
reg = <0x11>;
};
switch0phy1: ethernet-phy@12 {
switch0phy1: switch0phy1@12 {
reg = <0x12>;
};
switch0phy2: ethernet-phy@13 {
switch0phy2: switch0phy2@13 {
reg = <0x13>;
};
switch0phy3: ethernet-phy@14 {
switch0phy3: switch0phy3@14 {
reg = <0x14>;
};
};
......
arch/arm64/boot/dts/marvell/cn9130-crb.dtsi
View file @ aad36cd3
......@@ -207,9 +207,11 @@ phy0: ethernet-phy@0 {
reg = <0>;
};
switch6: ethernet-switch@6 {
switch6: switch0@6 {
/* Actual device is MV88E6393X */
compatible = "marvell,mv88e6190";
#address-cells = <1>;
#size-cells = <0>;
reg = <6>;
interrupt-parent = <&cp0_gpio1>;
interrupts = <28 IRQ_TYPE_LEVEL_LOW>;
......@@ -218,59 +220,59 @@ switch6: ethernet-switch@6 {
dsa,member = <0 0>;
ethernet-ports {
ports {
#address-cells = <1>;
#size-cells = <0>;
ethernet-port@1 {
port@1 {
reg = <1>;
label = "p1";
phy-handle = <&switch0phy1>;
};
ethernet-port@2 {
port@2 {
reg = <2>;
label = "p2";
phy-handle = <&switch0phy2>;
};
ethernet-port@3 {
port@3 {
reg = <3>;
label = "p3";
phy-handle = <&switch0phy3>;
};
ethernet-port@4 {
port@4 {
reg = <4>;
label = "p4";
phy-handle = <&switch0phy4>;
};
ethernet-port@5 {
port@5 {
reg = <5>;
label = "p5";
phy-handle = <&switch0phy5>;
};
ethernet-port@6 {
port@6 {
reg = <6>;
label = "p6";
phy-handle = <&switch0phy6>;
};
ethernet-port@7 {
port@7 {
reg = <7>;
label = "p7";
phy-handle = <&switch0phy7>;
};
ethernet-port@8 {
port@8 {
reg = <8>;
label = "p8";
phy-handle = <&switch0phy8>;
};
ethernet-port@9 {
port@9 {
reg = <9>;
label = "p9";
phy-mode = "10gbase-r";
......@@ -278,7 +280,7 @@ ethernet-port@9 {
managed = "in-band-status";
};
ethernet-port@a {
port@a {
reg = <10>;
ethernet = <&cp0_eth0>;
phy-mode = "10gbase-r";
......@@ -291,35 +293,35 @@ mdio {
#address-cells = <1>;
#size-cells = <0>;
switch0phy1: ethernet-phy@1 {
switch0phy1: switch0phy1@1 {
reg = <0x1>;
};
switch0phy2: ethernet-phy@2 {
switch0phy2: switch0phy2@2 {
reg = <0x2>;
};
switch0phy3: ethernet-phy@3 {
switch0phy3: switch0phy3@3 {
reg = <0x3>;
};
switch0phy4: ethernet-phy@4 {
switch0phy4: switch0phy4@4 {
reg = <0x4>;
};
switch0phy5: ethernet-phy@5 {
switch0phy5: switch0phy5@5 {
reg = <0x5>;
};
switch0phy6: ethernet-phy@6 {
switch0phy6: switch0phy6@6 {
reg = <0x6>;
};
switch0phy7: ethernet-phy@7 {
switch0phy7: switch0phy7@7 {
reg = <0x7>;
};
switch0phy8: ethernet-phy@8 {
switch0phy8: switch0phy8@8 {
reg = <0x8>;
};
};
......
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