Commit abecec41 authored by Yash Shah's avatar Yash Shah Committed by David S. Miller

macb: bindings doc: update sifive fu540-c000 binding

As per the discussion with Nicolas Ferre[0], rename the compatible property
to a more appropriate and specific string.

[0] https://lore.kernel.org/netdev/CAJ2_jOFEVZQat0Yprg4hem4jRrqkB72FKSeQj4p8P5KA-+rgww@mail.gmail.com/Signed-off-by: default avatarYash Shah <yash.shah@sifive.com>
Acked-by: default avatarNicolas Ferre <nicolas.ferre@microchip.com>
Reviewed-by: default avatarPaul Walmsley <paul.walmsley@sifive.com>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent fdfc5c85
...@@ -15,10 +15,10 @@ Required properties: ...@@ -15,10 +15,10 @@ Required properties:
Use "atmel,sama5d4-gem" for the GEM IP (10/100) available on Atmel sama5d4 SoCs. Use "atmel,sama5d4-gem" for the GEM IP (10/100) available on Atmel sama5d4 SoCs.
Use "cdns,zynq-gem" Xilinx Zynq-7xxx SoC. Use "cdns,zynq-gem" Xilinx Zynq-7xxx SoC.
Use "cdns,zynqmp-gem" for Zynq Ultrascale+ MPSoC. Use "cdns,zynqmp-gem" for Zynq Ultrascale+ MPSoC.
Use "sifive,fu540-macb" for SiFive FU540-C000 SoC. Use "sifive,fu540-c000-gem" for SiFive FU540-C000 SoC.
Or the generic form: "cdns,emac". Or the generic form: "cdns,emac".
- reg: Address and length of the register set for the device - reg: Address and length of the register set for the device
For "sifive,fu540-macb", second range is required to specify the For "sifive,fu540-c000-gem", second range is required to specify the
address and length of the registers for GEMGXL Management block. address and length of the registers for GEMGXL Management block.
- interrupts: Should contain macb interrupt - interrupts: Should contain macb interrupt
- phy-mode: See ethernet.txt file in the same directory. - phy-mode: See ethernet.txt file in the same directory.
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