Commit ac4a9350 authored by Slava Grigorev's avatar Slava Grigorev Committed by Alex Deucher

drm/radeon: Fix "slow" audio over DP on DCE8+

DP audio is derived from the dfs clock.
Signed-off-by: default avatarSlava Grigorev <slava.grigorev@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
parent ee1782c3
......@@ -301,6 +301,22 @@ void dce6_dp_audio_set_dto(struct radeon_device *rdev,
* is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
*/
if (ASIC_IS_DCE8(rdev)) {
unsigned int div = (RREG32(DENTIST_DISPCLK_CNTL) &
DENTIST_DPREFCLK_WDIVIDER_MASK) >>
DENTIST_DPREFCLK_WDIVIDER_SHIFT;
if (div < 128 && div >= 96)
div -= 64;
else if (div >= 64)
div = div / 2 - 16;
else if (div >= 8)
div /= 4;
else
div = 0;
if (div)
clock = rdev->clock.gpupll_outputfreq * 10 / div;
WREG32(DCE8_DCCG_AUDIO_DTO1_PHASE, 24000);
WREG32(DCE8_DCCG_AUDIO_DTO1_MODULE, clock);
} else {
......
......@@ -268,6 +268,7 @@ struct radeon_clock {
uint32_t current_dispclk;
uint32_t dp_extclk;
uint32_t max_pixel_clock;
uint32_t gpupll_outputfreq;
};
/*
......
......@@ -1263,6 +1263,13 @@ bool radeon_atom_get_clock_info(struct drm_device *dev)
rdev->mode_info.firmware_flags =
le16_to_cpu(firmware_info->info.usFirmwareCapability.susAccess);
if (ASIC_IS_DCE8(rdev)) {
rdev->clock.gpupll_outputfreq =
le32_to_cpu(firmware_info->info_22.ulGPUPLL_OutputFreq);
if (rdev->clock.gpupll_outputfreq == 0)
rdev->clock.gpupll_outputfreq = 360000; /* 3.6 GHz */
}
return true;
}
......
......@@ -915,6 +915,11 @@
#define DCCG_AUDIO_DTO1_PHASE 0x05c0
#define DCCG_AUDIO_DTO1_MODULE 0x05c4
#define DENTIST_DISPCLK_CNTL 0x0490
# define DENTIST_DPREFCLK_WDIVIDER(x) (((x) & 0x7f) << 24)
# define DENTIST_DPREFCLK_WDIVIDER_MASK (0x7f << 24)
# define DENTIST_DPREFCLK_WDIVIDER_SHIFT 24
#define AFMT_AUDIO_SRC_CONTROL 0x713c
#define AFMT_AUDIO_SRC_SELECT(x) (((x) & 7) << 0)
/* AFMT_AUDIO_SRC_SELECT
......
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