Commit aca69344 authored by David Daney's avatar David Daney Committed by Ulf Hansson

mmc: cavium-octeon: Fix interrupt enable code

OCTEON SoCs with CIU3 do not have interrupt masking local to the MMC
bus interface.  Unfortunately, some even have a diagnostic register at
the same address of the enable register, which causes the interrupts
to fire immediately if stored to, thus breaking the driver.  The proper
action on these SoCs is not to touch this register.

Fixes: 01d95843 ("mmc: cavium: Add MMC support for Octeon SOCs.")
Signed-off-by: default avatarDavid Daney <david.daney@cavium.com>
[jglauber@cavium.com: removed point after subject line]
Signed-off-by: default avatarJan Glauber <jglauber@cavium.com>
Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
parent bae3dee0
...@@ -108,7 +108,7 @@ static void octeon_mmc_release_bus(struct cvm_mmc_host *host) ...@@ -108,7 +108,7 @@ static void octeon_mmc_release_bus(struct cvm_mmc_host *host)
static void octeon_mmc_int_enable(struct cvm_mmc_host *host, u64 val) static void octeon_mmc_int_enable(struct cvm_mmc_host *host, u64 val)
{ {
writeq(val, host->base + MIO_EMM_INT(host)); writeq(val, host->base + MIO_EMM_INT(host));
if (!host->dma_active || (host->dma_active && !host->has_ciu3)) if (!host->has_ciu3)
writeq(val, host->base + MIO_EMM_INT_EN(host)); writeq(val, host->base + MIO_EMM_INT_EN(host));
} }
......
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