Commit ad4e05b2 authored by Max Gurtovoy's avatar Max Gurtovoy Committed by Sagi Grimberg

nvme: add symbolic constants for CC identifiers

Signed-off-by: default avatarMax Gurtovoy <maxg@mellanox.com>
Reviewed-by: default avatarSagi Grimberg <sagi@grimberg.me>
Signed-off-by: default avatarChristoph Hellwig <hch@lst.de>
parent caaa15c5
...@@ -538,37 +538,37 @@ EXPORT_SYMBOL_GPL(nvmet_req_uninit); ...@@ -538,37 +538,37 @@ EXPORT_SYMBOL_GPL(nvmet_req_uninit);
static inline bool nvmet_cc_en(u32 cc) static inline bool nvmet_cc_en(u32 cc)
{ {
return cc & 0x1; return (cc >> NVME_CC_EN_SHIFT) & 0x1;
} }
static inline u8 nvmet_cc_css(u32 cc) static inline u8 nvmet_cc_css(u32 cc)
{ {
return (cc >> 4) & 0x7; return (cc >> NVME_CC_CSS_SHIFT) & 0x7;
} }
static inline u8 nvmet_cc_mps(u32 cc) static inline u8 nvmet_cc_mps(u32 cc)
{ {
return (cc >> 7) & 0xf; return (cc >> NVME_CC_MPS_SHIFT) & 0xf;
} }
static inline u8 nvmet_cc_ams(u32 cc) static inline u8 nvmet_cc_ams(u32 cc)
{ {
return (cc >> 11) & 0x7; return (cc >> NVME_CC_AMS_SHIFT) & 0x7;
} }
static inline u8 nvmet_cc_shn(u32 cc) static inline u8 nvmet_cc_shn(u32 cc)
{ {
return (cc >> 14) & 0x3; return (cc >> NVME_CC_SHN_SHIFT) & 0x3;
} }
static inline u8 nvmet_cc_iosqes(u32 cc) static inline u8 nvmet_cc_iosqes(u32 cc)
{ {
return (cc >> 16) & 0xf; return (cc >> NVME_CC_IOSQES_SHIFT) & 0xf;
} }
static inline u8 nvmet_cc_iocqes(u32 cc) static inline u8 nvmet_cc_iocqes(u32 cc)
{ {
return (cc >> 20) & 0xf; return (cc >> NVME_CC_IOCQES_SHIFT) & 0xf;
} }
static void nvmet_start_ctrl(struct nvmet_ctrl *ctrl) static void nvmet_start_ctrl(struct nvmet_ctrl *ctrl)
......
...@@ -135,16 +135,22 @@ enum { ...@@ -135,16 +135,22 @@ enum {
enum { enum {
NVME_CC_ENABLE = 1 << 0, NVME_CC_ENABLE = 1 << 0,
NVME_CC_CSS_NVM = 0 << 4, NVME_CC_CSS_NVM = 0 << 4,
NVME_CC_EN_SHIFT = 0,
NVME_CC_CSS_SHIFT = 4,
NVME_CC_MPS_SHIFT = 7, NVME_CC_MPS_SHIFT = 7,
NVME_CC_ARB_RR = 0 << 11, NVME_CC_AMS_SHIFT = 11,
NVME_CC_ARB_WRRU = 1 << 11, NVME_CC_SHN_SHIFT = 14,
NVME_CC_ARB_VS = 7 << 11, NVME_CC_IOSQES_SHIFT = 16,
NVME_CC_SHN_NONE = 0 << 14, NVME_CC_IOCQES_SHIFT = 20,
NVME_CC_SHN_NORMAL = 1 << 14, NVME_CC_ARB_RR = 0 << NVME_CC_AMS_SHIFT,
NVME_CC_SHN_ABRUPT = 2 << 14, NVME_CC_ARB_WRRU = 1 << NVME_CC_AMS_SHIFT,
NVME_CC_SHN_MASK = 3 << 14, NVME_CC_ARB_VS = 7 << NVME_CC_AMS_SHIFT,
NVME_CC_IOSQES = NVME_NVM_IOSQES << 16, NVME_CC_SHN_NONE = 0 << NVME_CC_SHN_SHIFT,
NVME_CC_IOCQES = NVME_NVM_IOCQES << 20, NVME_CC_SHN_NORMAL = 1 << NVME_CC_SHN_SHIFT,
NVME_CC_SHN_ABRUPT = 2 << NVME_CC_SHN_SHIFT,
NVME_CC_SHN_MASK = 3 << NVME_CC_SHN_SHIFT,
NVME_CC_IOSQES = NVME_NVM_IOSQES << NVME_CC_IOSQES_SHIFT,
NVME_CC_IOCQES = NVME_NVM_IOCQES << NVME_CC_IOCQES_SHIFT,
NVME_CSTS_RDY = 1 << 0, NVME_CSTS_RDY = 1 << 0,
NVME_CSTS_CFS = 1 << 1, NVME_CSTS_CFS = 1 << 1,
NVME_CSTS_NSSRO = 1 << 4, NVME_CSTS_NSSRO = 1 << 4,
......
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