Commit ae6df418 authored by Tarun Kanti DebBarma's avatar Tarun Kanti DebBarma Committed by Tony Lindgren

ARM: OMAP2+: dmtimer: cleanup fclk usage

With omap_hwmod_get_main_clk() now available, this can be passed to
clk_get() to extract the fclk and thus avoid construction of fclk name.
Corrected the timer fck name mis-match between clock44xx_data.c and
omap_hwmod_44xx_data.c. For other platforms this is already taken care.

Cc: Cousson, Benoit <b-cousson@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Kevin Hilman <khilman@ti.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: default avatarTarun Kanti DebBarma <tarun.kanti@ti.com>
Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
parent 68c9a95e
...@@ -3299,17 +3299,17 @@ static struct omap_clk omap44xx_clks[] = { ...@@ -3299,17 +3299,17 @@ static struct omap_clk omap44xx_clks[] = {
CLK(NULL, "smartreflex_core_fck", &smartreflex_core_fck, CK_443X), CLK(NULL, "smartreflex_core_fck", &smartreflex_core_fck, CK_443X),
CLK(NULL, "smartreflex_iva_fck", &smartreflex_iva_fck, CK_443X), CLK(NULL, "smartreflex_iva_fck", &smartreflex_iva_fck, CK_443X),
CLK(NULL, "smartreflex_mpu_fck", &smartreflex_mpu_fck, CK_443X), CLK(NULL, "smartreflex_mpu_fck", &smartreflex_mpu_fck, CK_443X),
CLK(NULL, "gpt1_fck", &timer1_fck, CK_443X), CLK(NULL, "timer1_fck", &timer1_fck, CK_443X),
CLK(NULL, "gpt10_fck", &timer10_fck, CK_443X), CLK(NULL, "timer10_fck", &timer10_fck, CK_443X),
CLK(NULL, "gpt11_fck", &timer11_fck, CK_443X), CLK(NULL, "timer11_fck", &timer11_fck, CK_443X),
CLK(NULL, "gpt2_fck", &timer2_fck, CK_443X), CLK(NULL, "timer2_fck", &timer2_fck, CK_443X),
CLK(NULL, "gpt3_fck", &timer3_fck, CK_443X), CLK(NULL, "timer3_fck", &timer3_fck, CK_443X),
CLK(NULL, "gpt4_fck", &timer4_fck, CK_443X), CLK(NULL, "timer4_fck", &timer4_fck, CK_443X),
CLK(NULL, "gpt5_fck", &timer5_fck, CK_443X), CLK(NULL, "timer5_fck", &timer5_fck, CK_443X),
CLK(NULL, "gpt6_fck", &timer6_fck, CK_443X), CLK(NULL, "timer6_fck", &timer6_fck, CK_443X),
CLK(NULL, "gpt7_fck", &timer7_fck, CK_443X), CLK(NULL, "timer7_fck", &timer7_fck, CK_443X),
CLK(NULL, "gpt8_fck", &timer8_fck, CK_443X), CLK(NULL, "timer8_fck", &timer8_fck, CK_443X),
CLK(NULL, "gpt9_fck", &timer9_fck, CK_443X), CLK(NULL, "timer9_fck", &timer9_fck, CK_443X),
CLK(NULL, "uart1_fck", &uart1_fck, CK_443X), CLK(NULL, "uart1_fck", &uart1_fck, CK_443X),
CLK(NULL, "uart2_fck", &uart2_fck, CK_443X), CLK(NULL, "uart2_fck", &uart2_fck, CK_443X),
CLK(NULL, "uart3_fck", &uart3_fck, CK_443X), CLK(NULL, "uart3_fck", &uart3_fck, CK_443X),
......
...@@ -168,8 +168,7 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer, ...@@ -168,8 +168,7 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
return -ENXIO; return -ENXIO;
/* After the dmtimer is using hwmod these clocks won't be needed */ /* After the dmtimer is using hwmod these clocks won't be needed */
sprintf(name, "gpt%d_fck", gptimer_id); timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh));
timer->fclk = clk_get(NULL, name);
if (IS_ERR(timer->fclk)) if (IS_ERR(timer->fclk))
return -ENODEV; return -ENODEV;
......
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