Commit aec65e48 authored by Felix Fietkau's avatar Felix Fietkau

mt76: unify channel survey update code

Host time is used to calculate the channel active time on mt7603 and mt7615.
Use the same on mt76x02 and move the lock to core code to get rid of some
duplicated code.
Signed-off-by: default avatarFelix Fietkau <nbd@nbd.name>
parent dcff8d4d
...@@ -416,13 +416,25 @@ mt76_channel_state(struct mt76_dev *dev, struct ieee80211_channel *c) ...@@ -416,13 +416,25 @@ mt76_channel_state(struct mt76_dev *dev, struct ieee80211_channel *c)
void mt76_update_survey(struct mt76_dev *dev) void mt76_update_survey(struct mt76_dev *dev)
{ {
struct mt76_channel_state *state; struct mt76_channel_state *state = dev->chan_state;
ktime_t cur_time;
if (!test_bit(MT76_STATE_RUNNING, &dev->state))
return;
spin_lock_bh(&dev->cc_lock);
if (dev->drv->update_survey) if (dev->drv->update_survey)
dev->drv->update_survey(dev); dev->drv->update_survey(dev);
cur_time = ktime_get_boottime();
state->cc_active += ktime_to_us(ktime_sub(cur_time,
dev->survey_time));
dev->survey_time = cur_time;
spin_unlock_bh(&dev->cc_lock);
if (dev->drv->drv_flags & MT_DRV_SW_RX_AIRTIME) { if (dev->drv->drv_flags & MT_DRV_SW_RX_AIRTIME) {
state = mt76_channel_state(dev, dev->chandef.chan);
spin_lock_bh(&dev->rx_lock); spin_lock_bh(&dev->rx_lock);
spin_lock(&dev->cc_lock); spin_lock(&dev->cc_lock);
state->cc_bss_rx += dev->cur_cc_bss_rx; state->cc_bss_rx += dev->cur_cc_bss_rx;
......
...@@ -1571,22 +1571,9 @@ void mt7603_update_channel(struct mt76_dev *mdev) ...@@ -1571,22 +1571,9 @@ void mt7603_update_channel(struct mt76_dev *mdev)
{ {
struct mt7603_dev *dev = container_of(mdev, struct mt7603_dev, mt76); struct mt7603_dev *dev = container_of(mdev, struct mt7603_dev, mt76);
struct mt76_channel_state *state; struct mt76_channel_state *state;
ktime_t cur_time;
u32 busy;
if (!test_bit(MT76_STATE_RUNNING, &dev->mt76.state))
return;
state = mdev->chan_state; state = mdev->chan_state;
busy = mt76_rr(dev, MT_MIB_STAT_CCA); state->cc_busy += mt76_rr(dev, MT_MIB_STAT_CCA);
spin_lock_bh(&dev->mt76.cc_lock);
cur_time = ktime_get_boottime();
state->cc_busy += busy;
state->cc_active += ktime_to_us(ktime_sub(cur_time,
dev->mt76.survey_time));
dev->mt76.survey_time = cur_time;
spin_unlock_bh(&dev->mt76.cc_lock);
} }
void void
......
...@@ -1263,23 +1263,11 @@ void mt7615_update_channel(struct mt76_dev *mdev) ...@@ -1263,23 +1263,11 @@ void mt7615_update_channel(struct mt76_dev *mdev)
{ {
struct mt7615_dev *dev = container_of(mdev, struct mt7615_dev, mt76); struct mt7615_dev *dev = container_of(mdev, struct mt7615_dev, mt76);
struct mt76_channel_state *state; struct mt76_channel_state *state;
ktime_t cur_time;
u32 busy;
if (!test_bit(MT76_STATE_RUNNING, &mdev->state))
return;
state = mdev->chan_state;
/* TODO: add DBDC support */ /* TODO: add DBDC support */
busy = mt76_get_field(dev, MT_MIB_SDR16(0), MT_MIB_BUSY_MASK); state = mdev->chan_state;
state->cc_busy += mt76_get_field(dev, MT_MIB_SDR16(0),
spin_lock_bh(&mdev->cc_lock); MT_MIB_BUSY_MASK);
cur_time = ktime_get_boottime();
state->cc_busy += busy;
state->cc_active += ktime_to_us(ktime_sub(cur_time,
mdev->survey_time));
mdev->survey_time = cur_time;
spin_unlock_bh(&mdev->cc_lock);
} }
void mt7615_mac_work(struct work_struct *work) void mt7615_mac_work(struct work_struct *work)
......
...@@ -19,10 +19,7 @@ mt76x0_set_channel(struct mt76x02_dev *dev, struct cfg80211_chan_def *chandef) ...@@ -19,10 +19,7 @@ mt76x0_set_channel(struct mt76x02_dev *dev, struct cfg80211_chan_def *chandef)
mt76_set_channel(&dev->mt76); mt76_set_channel(&dev->mt76);
mt76x0_phy_set_channel(dev, chandef); mt76x0_phy_set_channel(dev, chandef);
/* channel cycle counters read-and-clear */ mt76x02_mac_cc_reset(dev);
mt76_rr(dev, MT_CH_IDLE);
mt76_rr(dev, MT_CH_BUSY);
mt76x02_edcca_init(dev); mt76x02_edcca_init(dev);
if (mt76_is_mmio(dev)) { if (mt76_is_mmio(dev)) {
......
...@@ -984,17 +984,9 @@ void mt76x02_update_channel(struct mt76_dev *mdev) ...@@ -984,17 +984,9 @@ void mt76x02_update_channel(struct mt76_dev *mdev)
{ {
struct mt76x02_dev *dev = container_of(mdev, struct mt76x02_dev, mt76); struct mt76x02_dev *dev = container_of(mdev, struct mt76x02_dev, mt76);
struct mt76_channel_state *state; struct mt76_channel_state *state;
u32 active, busy;
state = mdev->chan_state; state = mdev->chan_state;
state->cc_busy += mt76_rr(dev, MT_CH_BUSY);
busy = mt76_rr(dev, MT_CH_BUSY);
active = busy + mt76_rr(dev, MT_CH_IDLE);
spin_lock_bh(&dev->mt76.cc_lock);
state->cc_busy += busy;
state->cc_active += active;
spin_unlock_bh(&dev->mt76.cc_lock);
} }
EXPORT_SYMBOL_GPL(mt76x02_update_channel); EXPORT_SYMBOL_GPL(mt76x02_update_channel);
...@@ -1152,6 +1144,16 @@ void mt76x02_mac_work(struct work_struct *work) ...@@ -1152,6 +1144,16 @@ void mt76x02_mac_work(struct work_struct *work)
MT_MAC_WORK_INTERVAL); MT_MAC_WORK_INTERVAL);
} }
void mt76x02_mac_cc_reset(struct mt76x02_dev *dev)
{
dev->mt76.survey_time = ktime_get_boottime();
/* channel cycle counters read-and-clear */
mt76_rr(dev, MT_CH_BUSY);
mt76_rr(dev, MT_CH_IDLE);
}
EXPORT_SYMBOL_GPL(mt76x02_mac_cc_reset);
void mt76x02_mac_set_bssid(struct mt76x02_dev *dev, u8 idx, const u8 *addr) void mt76x02_mac_set_bssid(struct mt76x02_dev *dev, u8 idx, const u8 *addr)
{ {
idx &= 7; idx &= 7;
......
...@@ -193,6 +193,7 @@ void mt76x02_tx_complete_skb(struct mt76_dev *mdev, enum mt76_txq_id qid, ...@@ -193,6 +193,7 @@ void mt76x02_tx_complete_skb(struct mt76_dev *mdev, enum mt76_txq_id qid,
void mt76x02_update_channel(struct mt76_dev *mdev); void mt76x02_update_channel(struct mt76_dev *mdev);
void mt76x02_mac_work(struct work_struct *work); void mt76x02_mac_work(struct work_struct *work);
void mt76x02_mac_cc_reset(struct mt76x02_dev *dev);
void mt76x02_mac_set_bssid(struct mt76x02_dev *dev, u8 idx, const u8 *addr); void mt76x02_mac_set_bssid(struct mt76x02_dev *dev, u8 idx, const u8 *addr);
int mt76x02_mac_set_beacon(struct mt76x02_dev *dev, u8 vif_idx, int mt76x02_mac_set_beacon(struct mt76x02_dev *dev, u8 vif_idx,
struct sk_buff *skb); struct sk_buff *skb);
......
...@@ -52,10 +52,7 @@ mt76x2_set_channel(struct mt76x02_dev *dev, struct cfg80211_chan_def *chandef) ...@@ -52,10 +52,7 @@ mt76x2_set_channel(struct mt76x02_dev *dev, struct cfg80211_chan_def *chandef)
mt76x2_mac_stop(dev, true); mt76x2_mac_stop(dev, true);
ret = mt76x2_phy_set_channel(dev, chandef); ret = mt76x2_phy_set_channel(dev, chandef);
/* channel cycle counters read-and-clear */ mt76x02_mac_cc_reset(dev);
mt76_rr(dev, MT_CH_IDLE);
mt76_rr(dev, MT_CH_BUSY);
mt76x02_dfs_init_params(dev); mt76x02_dfs_init_params(dev);
mt76x2_mac_resume(dev); mt76x2_mac_resume(dev);
......
...@@ -49,10 +49,7 @@ mt76x2u_set_channel(struct mt76x02_dev *dev, ...@@ -49,10 +49,7 @@ mt76x2u_set_channel(struct mt76x02_dev *dev,
err = mt76x2u_phy_set_channel(dev, chandef); err = mt76x2u_phy_set_channel(dev, chandef);
/* channel cycle counters read-and-clear */ mt76x02_mac_cc_reset(dev);
mt76_rr(dev, MT_CH_IDLE);
mt76_rr(dev, MT_CH_BUSY);
mt76x2_mac_resume(dev); mt76x2_mac_resume(dev);
clear_bit(MT76_RESET, &dev->mt76.state); clear_bit(MT76_RESET, &dev->mt76.state);
......
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