drm/amd/powerplay: implement set_mmhub_powergating_by_smu for Raven

mmhub PG is enabled by SMU FW only for Raven.
Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c

@@ -1026,6 +1026,11 @@ static int rv_read_sensor(struct pp_hwmgr *hwmgr, int idx,
 	return ret;
 }
 
+static int rv_set_mmhub_powergating_by_smu(struct pp_hwmgr *hwmgr)
+{
+	return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PowerGateMmHub);
+}
+
 static const struct pp_hwmgr_func rv_hwmgr_funcs = {
 	.backend_init = rv_hwmgr_backend_init,
 	.backend_fini = rv_hwmgr_backend_fini,
@@ -1059,6 +1064,7 @@ static const struct pp_hwmgr_func rv_hwmgr_funcs = {
 	.asic_setup = rv_setup_asic_task,
 	.power_state_set = rv_set_power_state_tasks,
 	.dynamic_state_management_disable = rv_disable_dpm_tasks,
+	.set_mmhub_powergating_by_smu = rv_set_mmhub_powergating_by_smu,
 };
 
 int rv_init_function_pointers(struct pp_hwmgr *hwmgr)

drivers/gpu/drm/amd/powerplay/inc/rv_ppsmc.h

@@ -80,7 +80,8 @@
 #define PPSMC_MSG_SetSoftMaxSocclkByFreq        0x32
 #define PPSMC_MSG_SetSoftMaxFclkByFreq          0x33
 #define PPSMC_MSG_SetSoftMaxVcn                 0x34
-#define PPSMC_Message_Count                     0x35
+#define PPSMC_MSG_PowerGateMmHub                0x35
+#define PPSMC_Message_Count                     0x36
 
 
 typedef uint16_t PPSMC_Result;