Commit b155f05d authored by Florian Fainelli's avatar Florian Fainelli

Merge tag 'bcm2835-dt-next-2017-03-30' into devicetree/fixes

This pull request brings back bcm2835 DT fixups from Baruch Siach that
got misplaced after a PR for 4.11 got rejected.
Signed-off-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
parents 2ea659a9 10b6c0c2
/ { / {
aliases { aliases {
ethernet = &ethernet; ethernet0 = &ethernet;
}; };
}; };
......
/ { / {
aliases { aliases {
ethernet = &ethernet; ethernet0 = &ethernet;
}; };
}; };
......
...@@ -198,8 +198,8 @@ i2c0_gpio0: i2c0_gpio0 { ...@@ -198,8 +198,8 @@ i2c0_gpio0: i2c0_gpio0 {
brcm,pins = <0 1>; brcm,pins = <0 1>;
brcm,function = <BCM2835_FSEL_ALT0>; brcm,function = <BCM2835_FSEL_ALT0>;
}; };
i2c0_gpio32: i2c0_gpio32 { i2c0_gpio28: i2c0_gpio28 {
brcm,pins = <32 34>; brcm,pins = <28 29>;
brcm,function = <BCM2835_FSEL_ALT0>; brcm,function = <BCM2835_FSEL_ALT0>;
}; };
i2c0_gpio44: i2c0_gpio44 { i2c0_gpio44: i2c0_gpio44 {
...@@ -295,20 +295,28 @@ uart0_gpio14: uart0_gpio14 { ...@@ -295,20 +295,28 @@ uart0_gpio14: uart0_gpio14 {
/* Separate from the uart0_gpio14 group /* Separate from the uart0_gpio14 group
* because it conflicts with spi1_gpio16, and * because it conflicts with spi1_gpio16, and
* people often run uart0 on the two pins * people often run uart0 on the two pins
* without flow contrl. * without flow control.
*/ */
uart0_ctsrts_gpio16: uart0_ctsrts_gpio16 { uart0_ctsrts_gpio16: uart0_ctsrts_gpio16 {
brcm,pins = <16 17>; brcm,pins = <16 17>;
brcm,function = <BCM2835_FSEL_ALT3>; brcm,function = <BCM2835_FSEL_ALT3>;
}; };
uart0_gpio30: uart0_gpio30 { uart0_ctsrts_gpio30: uart0_ctsrts_gpio30 {
brcm,pins = <30 31>; brcm,pins = <30 31>;
brcm,function = <BCM2835_FSEL_ALT3>; brcm,function = <BCM2835_FSEL_ALT3>;
}; };
uart0_ctsrts_gpio32: uart0_ctsrts_gpio32 { uart0_gpio32: uart0_gpio32 {
brcm,pins = <32 33>; brcm,pins = <32 33>;
brcm,function = <BCM2835_FSEL_ALT3>; brcm,function = <BCM2835_FSEL_ALT3>;
}; };
uart0_gpio36: uart0_gpio36 {
brcm,pins = <36 37>;
brcm,function = <BCM2835_FSEL_ALT2>;
};
uart0_ctsrts_gpio38: uart0_ctsrts_gpio38 {
brcm,pins = <38 39>;
brcm,function = <BCM2835_FSEL_ALT2>;
};
uart1_gpio14: uart1_gpio14 { uart1_gpio14: uart1_gpio14 {
brcm,pins = <14 15>; brcm,pins = <14 15>;
...@@ -326,10 +334,6 @@ uart1_ctsrts_gpio30: uart1_ctsrts_gpio30 { ...@@ -326,10 +334,6 @@ uart1_ctsrts_gpio30: uart1_ctsrts_gpio30 {
brcm,pins = <30 31>; brcm,pins = <30 31>;
brcm,function = <BCM2835_FSEL_ALT5>; brcm,function = <BCM2835_FSEL_ALT5>;
}; };
uart1_gpio36: uart1_gpio36 {
brcm,pins = <36 37 38 39>;
brcm,function = <BCM2835_FSEL_ALT2>;
};
uart1_gpio40: uart1_gpio40 { uart1_gpio40: uart1_gpio40 {
brcm,pins = <40 41>; brcm,pins = <40 41>;
brcm,function = <BCM2835_FSEL_ALT5>; brcm,function = <BCM2835_FSEL_ALT5>;
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment