Commit b2121170 authored by Kevin Hilman's avatar Kevin Hilman

Merge tag 'amlogic-clk-headers' into v4.12/dt64

Amlogic clock headers and DT binding updates for v4.12
- add clocks for I2S and Mali

# gpg: Signature made Tue Apr  4 16:07:50 2017 PDT using RSA key ID D3FBC665
# gpg: Good signature from "Kevin Hilman <khilman@kernel.org>" [ultimate]
# gpg:                 aka "Kevin Hilman <khilman@deeprootsystems.com>" [ultimate]
# gpg:                 aka "Kevin Hilman <khilman@gmail.com>" [ultimate]
# gpg:                 aka "Kevin Hilman <khilman@baylibre.com>" [ultimate]

* tag 'amlogic-clk-headers':
  dt-bindings: clock: gxbb-clkc: Add GXL compatible variant
  clk: meson-gxbb: Expose GP0 dt-bindings clock id
  clk: meson-gxbb: Add MALI clock IDS
  dt-bindings: clk: gxbb: expose i2s output clock gates
parents 6939db7e 92c2cc5d
...@@ -5,7 +5,8 @@ controllers within the SoC. ...@@ -5,7 +5,8 @@ controllers within the SoC.
Required Properties: Required Properties:
- compatible: should be "amlogic,gxbb-clkc" - compatible: should be "amlogic,gxbb-clkc" for GXBB SoC,
or "amlogic,gxl-clkc" for GXL and GXM SoC.
- reg: physical base address of the clock controller and length of memory - reg: physical base address of the clock controller and length of memory
mapped region. mapped region.
......
...@@ -177,7 +177,7 @@ ...@@ -177,7 +177,7 @@
/* CLKID_FCLK_DIV4 */ /* CLKID_FCLK_DIV4 */
#define CLKID_FCLK_DIV5 7 #define CLKID_FCLK_DIV5 7
#define CLKID_FCLK_DIV7 8 #define CLKID_FCLK_DIV7 8
#define CLKID_GP0_PLL 9 /* CLKID_GP0_PLL */
#define CLKID_MPEG_SEL 10 #define CLKID_MPEG_SEL 10
#define CLKID_MPEG_DIV 11 #define CLKID_MPEG_DIV 11
/* CLKID_CLK81 */ /* CLKID_CLK81 */
...@@ -206,16 +206,16 @@ ...@@ -206,16 +206,16 @@
#define CLKID_I2S_SPDIF 35 #define CLKID_I2S_SPDIF 35
/* CLKID_ETH */ /* CLKID_ETH */
#define CLKID_DEMUX 37 #define CLKID_DEMUX 37
#define CLKID_AIU_GLUE 38 /* CLKID_AIU_GLUE */
#define CLKID_IEC958 39 #define CLKID_IEC958 39
#define CLKID_I2S_OUT 40 /* CLKID_I2S_OUT */
#define CLKID_AMCLK 41 #define CLKID_AMCLK 41
#define CLKID_AIFIFO2 42 #define CLKID_AIFIFO2 42
#define CLKID_MIXER 43 #define CLKID_MIXER 43
#define CLKID_MIXER_IFACE 44 /* CLKID_MIXER_IFACE */
#define CLKID_ADC 45 #define CLKID_ADC 45
#define CLKID_BLKMV 46 #define CLKID_BLKMV 46
#define CLKID_AIU 47 /* CLKID_AIU */
#define CLKID_UART1 48 #define CLKID_UART1 48
#define CLKID_G2D 49 #define CLKID_G2D 49
/* CLKID_USB0 */ /* CLKID_USB0 */
...@@ -248,7 +248,7 @@ ...@@ -248,7 +248,7 @@
/* CLKID_GCLK_VENCI_INT0 */ /* CLKID_GCLK_VENCI_INT0 */
#define CLKID_GCLK_VENCI_INT 78 #define CLKID_GCLK_VENCI_INT 78
#define CLKID_DAC_CLK 79 #define CLKID_DAC_CLK 79
#define CLKID_AOCLK_GATE 80 /* CLKID_AOCLK_GATE */
#define CLKID_IEC958_GATE 81 #define CLKID_IEC958_GATE 81
#define CLKID_ENC480P 82 #define CLKID_ENC480P 82
#define CLKID_RNG1 83 #define CLKID_RNG1 83
...@@ -268,8 +268,15 @@ ...@@ -268,8 +268,15 @@
/* CLKID_SAR_ADC_CLK */ /* CLKID_SAR_ADC_CLK */
/* CLKID_SAR_ADC_SEL */ /* CLKID_SAR_ADC_SEL */
#define CLKID_SAR_ADC_DIV 99 #define CLKID_SAR_ADC_DIV 99
/* CLKID_MALI_0_SEL */
#define CLKID_MALI_0_DIV 101
/* CLKID_MALI_0 */
/* CLKID_MALI_1_SEL */
#define CLKID_MALI_1_DIV 104
/* CLKID_MALI_1 */
/* CLKID_MALI */
#define NR_CLKS 100 #define NR_CLKS 107
/* include the CLKIDs that have been made part of the stable DT binding */ /* include the CLKIDs that have been made part of the stable DT binding */
#include <dt-bindings/clock/gxbb-clkc.h> #include <dt-bindings/clock/gxbb-clkc.h>
......
...@@ -10,12 +10,17 @@ ...@@ -10,12 +10,17 @@
#define CLKID_FCLK_DIV2 4 #define CLKID_FCLK_DIV2 4
#define CLKID_FCLK_DIV3 5 #define CLKID_FCLK_DIV3 5
#define CLKID_FCLK_DIV4 6 #define CLKID_FCLK_DIV4 6
#define CLKID_GP0_PLL 9
#define CLKID_CLK81 12 #define CLKID_CLK81 12
#define CLKID_MPLL2 15 #define CLKID_MPLL2 15
#define CLKID_SPI 34 #define CLKID_SPI 34
#define CLKID_I2C 22 #define CLKID_I2C 22
#define CLKID_SAR_ADC 23 #define CLKID_SAR_ADC 23
#define CLKID_ETH 36 #define CLKID_ETH 36
#define CLKID_AIU_GLUE 38
#define CLKID_I2S_OUT 40
#define CLKID_MIXER_IFACE 44
#define CLKID_AIU 47
#define CLKID_USB0 50 #define CLKID_USB0 50
#define CLKID_USB1 51 #define CLKID_USB1 51
#define CLKID_USB 55 #define CLKID_USB 55
...@@ -24,11 +29,17 @@ ...@@ -24,11 +29,17 @@
#define CLKID_USB0_DDR_BRIDGE 65 #define CLKID_USB0_DDR_BRIDGE 65
#define CLKID_SANA 69 #define CLKID_SANA 69
#define CLKID_GCLK_VENCI_INT0 77 #define CLKID_GCLK_VENCI_INT0 77
#define CLKID_AOCLK_GATE 80
#define CLKID_AO_I2C 93 #define CLKID_AO_I2C 93
#define CLKID_SD_EMMC_A 94 #define CLKID_SD_EMMC_A 94
#define CLKID_SD_EMMC_B 95 #define CLKID_SD_EMMC_B 95
#define CLKID_SD_EMMC_C 96 #define CLKID_SD_EMMC_C 96
#define CLKID_SAR_ADC_CLK 97 #define CLKID_SAR_ADC_CLK 97
#define CLKID_SAR_ADC_SEL 98 #define CLKID_SAR_ADC_SEL 98
#define CLKID_MALI_0_SEL 100
#define CLKID_MALI_0 102
#define CLKID_MALI_1_SEL 103
#define CLKID_MALI_1 105
#define CLKID_MALI 106
#endif /* __GXBB_CLKC_H */ #endif /* __GXBB_CLKC_H */
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