Commit b22ef2a0 authored by Laxman Dewangan's avatar Laxman Dewangan Committed by Linus Walleij

pinctrl: tegra: Correctly check the supported configuration

The pincontrol registers of Tegra chips has multiple filed per
registers. There is two type of registers mux and drive. All
configurations belongs to one of these registers.

If any configurations are supported then <config>_bit is set to
bit position of these registers otherwise -1 to not support it.
The member is defined as
	s32 <config>_bit:6;

So if config is not supported ifor given SoC then it is set to -1
in soc pinmmux table.
In common driver code, to find out that given config is supported
or not, it is checked as:

s8 bit = <config>_bit;
if (bit > 31) {
	/* Not supported config */
}

But in this case, bit is s8 and hence for non supporting it is -1.

Correct the check as:
if (bit < 0) {
	/* Not supported config */
}

Fixes: e4c02dce ("pinctrl: tegra: use signed bitfields for optional fields")
Signed-off-by: default avatarLaxman Dewangan <ldewangan@nvidia.com>
Acked-by: default avatarStephen Warren <swarren@nvidia.com>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent 468c234f
...@@ -417,7 +417,7 @@ static int tegra_pinconf_reg(struct tegra_pmx *pmx, ...@@ -417,7 +417,7 @@ static int tegra_pinconf_reg(struct tegra_pmx *pmx,
return -ENOTSUPP; return -ENOTSUPP;
} }
if (*reg < 0 || *bit > 31) { if (*reg < 0 || *bit < 0) {
if (report_err) { if (report_err) {
const char *prop = "unknown"; const char *prop = "unknown";
int i; int i;
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment