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Commit b25d72e9 authored by Tom Rini's avatar Tom Rini
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Merge kernel.crashing.org:/home/trini/work/kernel/devel/linux-2.6-boot 

into kernel.crashing.org:/home/trini/work/kernel/pristine/for-linus-ppc
parents 20ab1462 2a790ca1
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Showing with 1290 additions and 653 deletions
arch/ppc/Kconfig
View file @ b25d72e9
......@@ -609,7 +609,7 @@ config PPC_OF
config PPC_GEN550
bool
depends on SANDPOINT || MCPN765 || SPRUCE
depends on SANDPOINT || MCPN765 || SPRUCE || PPLUS
default y
config FORCE
......
arch/ppc/configs/pplus_defconfig
View file @ b25d72e9
This diff is collapsed.
arch/ppc/platforms/Makefile
View file @ b25d72e9
......@@ -41,7 +41,7 @@ obj-$(CONFIG_MVME5100) += mvme5100_setup.o mvme5100_pci.o
obj-$(CONFIG_PAL4) += pal4_setup.o pal4_pci.o
obj-$(CONFIG_PCORE) += pcore_setup.o pcore_pci.o
obj-$(CONFIG_POWERPMC250) += powerpmc250.o
obj-$(CONFIG_PPLUS) += pplus_pci.o pplus_setup.o
obj-$(CONFIG_PPLUS) += pplus.o
obj-$(CONFIG_PRPMC750) += prpmc750_setup.o prpmc750_pci.o
obj-$(CONFIG_PRPMC800) += prpmc800_setup.o prpmc800_pci.o
obj-$(CONFIG_SANDPOINT) += sandpoint.o
......
arch/ppc/platforms/pplus.h 0 → 100644
View file @ b25d72e9
/*
* arch/ppc/platforms/pplus.h
*
* Definitions for Motorola MCG Falcon/Raven & HAWK North Bridge & Memory ctlr.
*
* Author: Mark A. Greerinclude/asm-ppc/hawk.h
* mgreer@mvista.com
*
* Modified by Randy Vinson (rvinson@mvista.com)
*
* 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*/
#ifndef __PPC_PPLUS_H
#define __PPC_PPLUS_H
#include <asm/io.h>
/*
* Due to limiations imposed by legacy hardware (primaryily IDE controllers),
* the PPLUS boards operate using a PReP address map.
*
* From Processor (physical) -> PCI:
* PCI Mem Space: 0xc0000000 - 0xfe000000 -> 0x00000000 - 0x3e000000 (768 MB)
* PCI I/O Space: 0x80000000 - 0x90000000 -> 0x00000000 - 0x10000000 (256 MB)
* Note: Must skip 0xfe000000-0xfe400000 for CONFIG_HIGHMEM/PKMAP area
*
* From PCI -> Processor (physical):
* System Memory: 0x80000000 -> 0x00000000
*/
#define PPLUS_ISA_MEM_BASE PREP_ISA_MEM_BASE
#define PPLUS_ISA_IO_BASE PREP_ISA_IO_BASE
/* PCI Memory space mapping info */
#define PPLUS_PCI_MEM_SIZE 0x30000000U
#define PPLUS_PROC_PCI_MEM_START PPLUS_ISA_MEM_BASE
#define PPLUS_PROC_PCI_MEM_END (PPLUS_PROC_PCI_MEM_START + \
PPLUS_PCI_MEM_SIZE - 1)
#define PPLUS_PCI_MEM_START 0x00000000U
#define PPLUS_PCI_MEM_END (PPLUS_PCI_MEM_START + \
PPLUS_PCI_MEM_SIZE - 1)
/* PCI I/O space mapping info */
#define PPLUS_PCI_IO_SIZE 0x10000000U
#define PPLUS_PROC_PCI_IO_START PPLUS_ISA_IO_BASE
#define PPLUS_PROC_PCI_IO_END (PPLUS_PROC_PCI_IO_START + \
PPLUS_PCI_IO_SIZE - 1)
#define PPLUS_PCI_IO_START 0x00000000U
#define PPLUS_PCI_IO_END (PPLUS_PCI_IO_START + \
PPLUS_PCI_IO_SIZE - 1)
/* System memory mapping info */
#define PPLUS_PCI_DRAM_OFFSET PREP_PCI_DRAM_OFFSET
#define PPLUS_PCI_PHY_MEM_OFFSET (PPLUS_ISA_MEM_BASE-PPLUS_PCI_MEM_START)
/* Define base addresses for important sets of registers */
#define PPLUS_HAWK_SMC_BASE 0xfef80000U
#define PPLUS_HAWK_PPC_REG_BASE 0xfeff0000U
#define PPLUS_SYS_CONFIG_REG 0xfef80400U
#define PPLUS_L2_CONTROL_REG 0x8000081cU
#define PPLUS_VGA_MEM_BASE 0xf0000000U
extern int pplus_init(struct pci_controller *hose,
unsigned int ppc_reg_base, unsigned long processor_pci_mem_start,
unsigned long processor_pci_mem_end,
unsigned long processor_pci_io_start,
unsigned long processor_pci_io_end,
unsigned long processor_mpic_base);
extern unsigned long pplus_get_mem_size(unsigned int smc_base);
extern int pplus_mpic_init(unsigned int pci_mem_offset);
#endif /* __PPC_PPLUS_H */
arch/ppc/platforms/pplus_setup.c deleted 100644 → 0
View file @ 20ab1462
This diff is collapsed.
arch/ppc/syslib/pplus_common.c
View file @ b25d72e9
......@@ -21,7 +21,7 @@
#include <asm/pci.h>
#include <asm/pci-bridge.h>
#include <asm/open_pic.h>
#include <asm/pplus.h>
#include <asm/hawk.h>
/*
* The Falcon/Raven and HAWK has 4 sets of registers:
......@@ -95,10 +95,10 @@ pplus_init(struct pci_controller *hose,
/*
* Disable previous PPC->PCI mappings.
*/
out_be32((uint *)(ppc_reg_base + PPLUS_PPC_XSOFF0_OFF), 0x00000000);
out_be32((uint *)(ppc_reg_base + PPLUS_PPC_XSOFF1_OFF), 0x00000000);
out_be32((uint *)(ppc_reg_base + PPLUS_PPC_XSOFF2_OFF), 0x00000000);
out_be32((uint *)(ppc_reg_base + PPLUS_PPC_XSOFF3_OFF), 0x00000000);
out_be32((uint *)(ppc_reg_base + HAWK_PPC_XSOFF0_OFF), 0x00000000);
out_be32((uint *)(ppc_reg_base + HAWK_PPC_XSOFF1_OFF), 0x00000000);
out_be32((uint *)(ppc_reg_base + HAWK_PPC_XSOFF2_OFF), 0x00000000);
out_be32((uint *)(ppc_reg_base + HAWK_PPC_XSOFF3_OFF), 0x00000000);
/*
* Program the XSADD/XSOFF registers to set up the PCI Mem & I/O
......@@ -113,21 +113,23 @@ pplus_init(struct pci_controller *hose,
/* Set up PPC->PCI Mem mapping */
addr = processor_pci_mem_start | (processor_pci_mem_end >> 16);
offset = (hose->mem_space.start - processor_pci_mem_start) | 0xd2;
out_be32((uint *)(ppc_reg_base + PPLUS_PPC_XSADD0_OFF), addr);
out_be32((uint *)(ppc_reg_base + PPLUS_PPC_XSOFF0_OFF), offset);
out_be32((uint *)(ppc_reg_base + HAWK_PPC_XSADD0_OFF), addr);
out_be32((uint *)(ppc_reg_base + HAWK_PPC_XSOFF0_OFF), offset);
/* Set up PPC->MPIC mapping on the bridge */
addr = processor_mpic_base |
(((processor_mpic_base + PPLUS_MPIC_SIZE) >> 16) - 1);
offset = 0xc2; /* No write posting for this PCI Mem space */
out_be32((uint *)(ppc_reg_base + PPLUS_PPC_XSADD1_OFF), addr);
out_be32((uint *)(ppc_reg_base + PPLUS_PPC_XSOFF1_OFF), offset);
(((processor_mpic_base + HAWK_MPIC_SIZE) >> 16) - 1);
/* No write posting for this PCI Mem space */
offset = (hose->mem_space.start - processor_pci_mem_start) | 0xc2;
out_be32((uint *)(ppc_reg_base + HAWK_PPC_XSADD1_OFF), addr);
out_be32((uint *)(ppc_reg_base + HAWK_PPC_XSOFF1_OFF), offset);
/* Set up PPC->PCI I/O mapping -- Contiguous I/O space */
addr = processor_pci_io_start | (processor_pci_io_end >> 16);
offset = (hose->io_space.start - processor_pci_io_start) | 0xc0;
out_be32((uint *)(ppc_reg_base + PPLUS_PPC_XSADD3_OFF), addr);
out_be32((uint *)(ppc_reg_base + PPLUS_PPC_XSOFF3_OFF), offset);
out_be32((uint *)(ppc_reg_base + HAWK_PPC_XSADD3_OFF), addr);
out_be32((uint *)(ppc_reg_base + HAWK_PPC_XSOFF3_OFF), offset);
hose->io_base_virt = (void *)ioremap(processor_pci_io_start,
(processor_pci_io_end - processor_pci_io_start + 1));
......@@ -137,8 +139,8 @@ pplus_init(struct pci_controller *hose,
* The PCI config addr/data pair based on start addr of PCI I/O space.
*/
setup_indirect_pci(hose,
processor_pci_io_start + PPLUS_PCI_CONFIG_ADDR_OFF,
processor_pci_io_start + PPLUS_PCI_CONFIG_DATA_OFF);
processor_pci_io_start + HAWK_PCI_CONFIG_ADDR_OFF,
processor_pci_io_start + HAWK_PCI_CONFIG_DATA_OFF);
/*
* Disable previous PCI->PPC mappings.
......@@ -161,10 +163,12 @@ pplus_init(struct pci_controller *hose,
0,
PCI_DEVFN(0,0),
PCI_BASE_ADDRESS_1,
processor_mpic_base | 0x0);
(processor_mpic_base -
processor_pci_mem_start +
hose->mem_space.start) | 0x0);
/* Map MPIC into vitual memory */
OpenPIC_Addr = ioremap(processor_mpic_base, PPLUS_MPIC_SIZE);
OpenPIC_Addr = ioremap(processor_mpic_base, HAWK_MPIC_SIZE);
return 0;
}
......@@ -181,14 +185,14 @@ pplus_init(struct pci_controller *hose,
#define MB (1024*1024)
static uint reg_offset_table[] __initdata = {
PPLUS_SMC_RAM_A_SIZE_REG_OFF,
PPLUS_SMC_RAM_B_SIZE_REG_OFF,
PPLUS_SMC_RAM_C_SIZE_REG_OFF,
PPLUS_SMC_RAM_D_SIZE_REG_OFF,
PPLUS_SMC_RAM_E_SIZE_REG_OFF,
PPLUS_SMC_RAM_F_SIZE_REG_OFF,
PPLUS_SMC_RAM_G_SIZE_REG_OFF,
PPLUS_SMC_RAM_H_SIZE_REG_OFF
HAWK_SMC_RAM_A_SIZE_REG_OFF,
HAWK_SMC_RAM_B_SIZE_REG_OFF,
HAWK_SMC_RAM_C_SIZE_REG_OFF,
HAWK_SMC_RAM_D_SIZE_REG_OFF,
HAWK_SMC_RAM_E_SIZE_REG_OFF,
HAWK_SMC_RAM_F_SIZE_REG_OFF,
HAWK_SMC_RAM_G_SIZE_REG_OFF,
HAWK_SMC_RAM_H_SIZE_REG_OFF
};
static uint falcon_size_table[] __initdata = {
......@@ -246,13 +250,13 @@ pplus_get_mem_size(uint smc_base)
size_table_entries = sizeof(falcon_size_table) /
sizeof(falcon_size_table[0]);
reg_limit = PPLUS_FALCON_SMC_REG_COUNT;
reg_limit = FALCON_SMC_REG_COUNT;
}
else if (vend_dev_id == PCI_DEVICE_ID_MOTOROLA_HAWK) {
size_table = hawk_size_table;
size_table_entries = sizeof(hawk_size_table) /
sizeof(hawk_size_table[0]);
reg_limit = PPLUS_HAWK_SMC_REG_COUNT;
reg_limit = HAWK_SMC_REG_COUNT;
}
else {
printk("pplus_get_mem_size: %s (0x%x)\n",
......
include/asm-ppc/hawk.h 0 → 100644
View file @ b25d72e9
/*
* include/asm-ppc/hawk.h
*
* Support functions for MCG Falcon/Raven & HAWK North Bridge & Memory ctlr.
*
* Author: Mark A. Greer
* mgreer@mvista.com
*
* Modified by Randy Vinson (rvinson@mvista.com)
*
* 2001,2004 (c) MontaVista, Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*/
#ifndef __ASMPPC_HAWK_H
#define __ASMPPC_HAWK_H
#include <asm/pci-bridge.h>
#include <asm/hawk_defs.h>
extern int hawk_init(struct pci_controller *hose,
unsigned int ppc_reg_base, unsigned long processor_pci_mem_start,
unsigned long processor_pci_mem_end,
unsigned long processor_pci_io_start,
unsigned long processor_pci_io_end,
unsigned long processor_mpic_base);
extern unsigned long hawk_get_mem_size(unsigned int smc_base);
extern int hawk_mpic_init(unsigned int pci_mem_offset);
#endif /* __ASMPPC_PPLUS_H */
include/asm-ppc/pplus.h → include/asm-ppc/hawk_defs.h
View file @ b25d72e9
/*
* include/asm-ppc/pplus.h
* include/asm-ppc/hawk_defs.h
*
* Definitions for Motorola MCG Falcon/Raven & HAWK North Bridge & Memory ctlr.
*
* Author: Mark A. Greer
* mgreer@mvista.com
*
* 2001 (c) MontaVista, Software, Inc. This file is licensed under
* Modified by Randy Vinson (rvinson@mvista.com)
*
* 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*/
#ifndef __ASMPPC_PPLUS_H
#define __ASMPPC_PPLUS_H
#ifndef __ASMPPC_HAWK_DEFS_H
#define __ASMPPC_HAWK_DEFS_H
#include <asm/pci-bridge.h>
......@@ -27,66 +29,48 @@
* 4) System Memory Controller (SMC) registers.
*/
#define PPLUS_RAVEN_VEND_DEV_ID 0x48011057
#define PPLUS_HAWK_VEND_DEV_ID 0x48031057
#define PPLUS_PCI_CONFIG_ADDR_OFF 0x00000cf8
#define PPLUS_PCI_CONFIG_DATA_OFF 0x00000cfc
#define HAWK_PCI_CONFIG_ADDR_OFF 0x00000cf8
#define HAWK_PCI_CONFIG_DATA_OFF 0x00000cfc
#define PPLUS_MPIC_SIZE 0x00040000U
#define PPLUS_SMC_SIZE 0x00001000U
#define HAWK_MPIC_SIZE 0x00040000U
#define HAWK_SMC_SIZE 0x00001000U
/*
* Define PPC register offsets.
*/
#define PPLUS_PPC_XSADD0_OFF 0x40
#define PPLUS_PPC_XSOFF0_OFF 0x44
#define PPLUS_PPC_XSADD1_OFF 0x48
#define PPLUS_PPC_XSOFF1_OFF 0x4c
#define PPLUS_PPC_XSADD2_OFF 0x50
#define PPLUS_PPC_XSOFF2_OFF 0x54
#define PPLUS_PPC_XSADD3_OFF 0x58
#define PPLUS_PPC_XSOFF3_OFF 0x5c
#define HAWK_PPC_XSADD0_OFF 0x40
#define HAWK_PPC_XSOFF0_OFF 0x44
#define HAWK_PPC_XSADD1_OFF 0x48
#define HAWK_PPC_XSOFF1_OFF 0x4c
#define HAWK_PPC_XSADD2_OFF 0x50
#define HAWK_PPC_XSOFF2_OFF 0x54
#define HAWK_PPC_XSADD3_OFF 0x58
#define HAWK_PPC_XSOFF3_OFF 0x5c
/*
* Define PCI register offsets.
*/
#define PPLUS_PCI_PSADD0_OFF 0x80
#define PPLUS_PCI_PSOFF0_OFF 0x84
#define PPLUS_PCI_PSADD1_OFF 0x88
#define PPLUS_PCI_PSOFF1_OFF 0x8c
#define PPLUS_PCI_PSADD2_OFF 0x90
#define PPLUS_PCI_PSOFF2_OFF 0x94
#define PPLUS_PCI_PSADD3_OFF 0x98
#define PPLUS_PCI_PSOFF3_OFF 0x9c
#define HAWK_PCI_PSADD0_OFF 0x80
#define HAWK_PCI_PSOFF0_OFF 0x84
#define HAWK_PCI_PSADD1_OFF 0x88
#define HAWK_PCI_PSOFF1_OFF 0x8c
#define HAWK_PCI_PSADD2_OFF 0x90
#define HAWK_PCI_PSOFF2_OFF 0x94
#define HAWK_PCI_PSADD3_OFF 0x98
#define HAWK_PCI_PSOFF3_OFF 0x9c
/*
* Define the System Memory Controller (SMC) register offsets.
*/
#define PPLUS_SMC_RAM_A_SIZE_REG_OFF 0x10
#define PPLUS_SMC_RAM_B_SIZE_REG_OFF 0x11
#define PPLUS_SMC_RAM_C_SIZE_REG_OFF 0x12
#define PPLUS_SMC_RAM_D_SIZE_REG_OFF 0x13
#define PPLUS_SMC_RAM_E_SIZE_REG_OFF 0xc0 /* HAWK Only */
#define PPLUS_SMC_RAM_F_SIZE_REG_OFF 0xc1 /* HAWK Only */
#define PPLUS_SMC_RAM_G_SIZE_REG_OFF 0xc2 /* HAWK Only */
#define PPLUS_SMC_RAM_H_SIZE_REG_OFF 0xc3 /* HAWK Only */
#define PPLUS_FALCON_SMC_REG_COUNT 4
#define PPLUS_HAWK_SMC_REG_COUNT 8
int pplus_init(struct pci_controller *hose,
uint ppc_reg_base,
ulong processor_pci_mem_start,
ulong processor_pci_mem_end,
ulong processor_pci_io_start,
ulong processor_pci_io_end,
ulong processor_mpic_base);
unsigned long pplus_get_mem_size(uint smc_base);
int pplus_mpic_init(unsigned int pci_mem_offset);
#endif /* __ASMPPC_PPLUS_H */
#define HAWK_SMC_RAM_A_SIZE_REG_OFF 0x10
#define HAWK_SMC_RAM_B_SIZE_REG_OFF 0x11
#define HAWK_SMC_RAM_C_SIZE_REG_OFF 0x12
#define HAWK_SMC_RAM_D_SIZE_REG_OFF 0x13
#define HAWK_SMC_RAM_E_SIZE_REG_OFF 0xc0 /* HAWK Only */
#define HAWK_SMC_RAM_F_SIZE_REG_OFF 0xc1 /* HAWK Only */
#define HAWK_SMC_RAM_G_SIZE_REG_OFF 0xc2 /* HAWK Only */
#define HAWK_SMC_RAM_H_SIZE_REG_OFF 0xc3 /* HAWK Only */
#define FALCON_SMC_REG_COUNT 4
#define HAWK_SMC_REG_COUNT 8
#endif /* __ASMPPC_HAWK_DEFS_H */
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