Commit b29dad9b authored by Muralidhara M K's avatar Muralidhara M K Committed by Borislav Petkov (AMD)

EDAC/amd64: Split read_base_mask() into dct/umc functions

Call them from their respective hw_info_get() paths.

Call the new functions after the setting the chip select base and mask
counts, since those are need to read the correct number of chip select
base and mask registers. And call the new functions before the remaining
set up, because the base and mask register values will be needed later.

  [Yazen: Rebased/reworked patch and reworded commit message. ]
Signed-off-by: default avatarMuralidhara M K <muralidhara.mk@amd.com>
Co-developed-by: default avatarNaveen Krishna Chatradhi <naveenkrishna.chatradhi@amd.com>
Signed-off-by: default avatarNaveen Krishna Chatradhi <naveenkrishna.chatradhi@amd.com>
Co-developed-by: default avatarYazen Ghannam <yazen.ghannam@amd.com>
Signed-off-by: default avatarYazen Ghannam <yazen.ghannam@amd.com>
Signed-off-by: default avatarBorislav Petkov (AMD) <bp@alien8.de>
Link: https://lore.kernel.org/r/20230127170419.1824692-14-yazen.ghannam@amd.com
parent 637f60ef
...@@ -1638,7 +1638,7 @@ static void umc_prep_chip_selects(struct amd64_pvt *pvt) ...@@ -1638,7 +1638,7 @@ static void umc_prep_chip_selects(struct amd64_pvt *pvt)
} }
} }
static void read_umc_base_mask(struct amd64_pvt *pvt) static void umc_read_base_mask(struct amd64_pvt *pvt)
{ {
u32 umc_base_reg, umc_base_reg_sec; u32 umc_base_reg, umc_base_reg_sec;
u32 umc_mask_reg, umc_mask_reg_sec; u32 umc_mask_reg, umc_mask_reg_sec;
...@@ -1692,13 +1692,10 @@ static void read_umc_base_mask(struct amd64_pvt *pvt) ...@@ -1692,13 +1692,10 @@ static void read_umc_base_mask(struct amd64_pvt *pvt)
/* /*
* Function 2 Offset F10_DCSB0; read in the DCS Base and DCS Mask registers * Function 2 Offset F10_DCSB0; read in the DCS Base and DCS Mask registers
*/ */
static void read_dct_base_mask(struct amd64_pvt *pvt) static void dct_read_base_mask(struct amd64_pvt *pvt)
{ {
int cs; int cs;
if (pvt->umc)
return read_umc_base_mask(pvt);
for_each_chip_select(cs, 0, pvt) { for_each_chip_select(cs, 0, pvt) {
int reg0 = DCSB0 + (cs * 4); int reg0 = DCSB0 + (cs * 4);
int reg1 = DCSB1 + (cs * 4); int reg1 = DCSB1 + (cs * 4);
...@@ -3185,7 +3182,6 @@ static void read_mc_regs(struct amd64_pvt *pvt) ...@@ -3185,7 +3182,6 @@ static void read_mc_regs(struct amd64_pvt *pvt)
} }
skip: skip:
read_dct_base_mask(pvt);
determine_memory_type(pvt); determine_memory_type(pvt);
...@@ -3666,6 +3662,7 @@ static int dct_hw_info_get(struct amd64_pvt *pvt) ...@@ -3666,6 +3662,7 @@ static int dct_hw_info_get(struct amd64_pvt *pvt)
return ret; return ret;
dct_prep_chip_selects(pvt); dct_prep_chip_selects(pvt);
dct_read_base_mask(pvt);
read_mc_regs(pvt); read_mc_regs(pvt);
return 0; return 0;
...@@ -3678,6 +3675,7 @@ static int umc_hw_info_get(struct amd64_pvt *pvt) ...@@ -3678,6 +3675,7 @@ static int umc_hw_info_get(struct amd64_pvt *pvt)
return -ENOMEM; return -ENOMEM;
umc_prep_chip_selects(pvt); umc_prep_chip_selects(pvt);
umc_read_base_mask(pvt);
read_mc_regs(pvt); read_mc_regs(pvt);
return 0; return 0;
......
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