Commit b34a1a71 authored by Joshua Kinard's avatar Joshua Kinard Committed by Thomas Bogendoerfer

MIPS: SGI-IP30: Reorder the macros in war.h

Fix the ordering of the macros in arch/mips/mach-ip30/war.h to match
those in arch/mips/mach-ip27/war.h.
Signed-off-by: default avatarJoshua Kinard <kumba@gentoo.org>
Signed-off-by: default avatarThomas Bogendoerfer <tsbogend@alpha.franken.de>
parent ec7a9318
...@@ -8,18 +8,17 @@ ...@@ -8,18 +8,17 @@
#define R4600_V1_INDEX_ICACHEOP_WAR 0 #define R4600_V1_INDEX_ICACHEOP_WAR 0
#define R4600_V1_HIT_CACHEOP_WAR 0 #define R4600_V1_HIT_CACHEOP_WAR 0
#define R4600_V2_HIT_CACHEOP_WAR 0 #define R4600_V2_HIT_CACHEOP_WAR 0
#define MIPS_CACHE_SYNC_WAR 0
#define BCM1250_M3_WAR 0 #define BCM1250_M3_WAR 0
#define SIBYTE_1956_WAR 0 #define SIBYTE_1956_WAR 0
#define MIPS4K_ICACHE_REFILL_WAR 0 #define MIPS4K_ICACHE_REFILL_WAR 0
#define MIPS34K_MISSED_ITLB_WAR 0 #define MIPS_CACHE_SYNC_WAR 0
#define TX49XX_ICACHE_INDEX_INV_WAR 0 #define TX49XX_ICACHE_INDEX_INV_WAR 0
#define ICACHE_REFILLS_WORKAROUND_WAR 0 #define ICACHE_REFILLS_WORKAROUND_WAR 0
#ifdef CONFIG_CPU_R10000 #ifdef CONFIG_CPU_R10000
#define R10000_LLSC_WAR 1 #define R10000_LLSC_WAR 1
#else #else
#define R10000_LLSC_WAR 0 #define R10000_LLSC_WAR 0
#endif #endif
#define MIPS34K_MISSED_ITLB_WAR 0
#endif /* __ASM_MIPS_MACH_IP30_WAR_H */ #endif /* __ASM_MIPS_MACH_IP30_WAR_H */
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