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Kirill Smelkov
linux
Commits
b3a0f501
Commit
b3a0f501
authored
May 27, 2004
by
Ganesh Venkatesan
Committed by
Jeff Garzik
May 27, 2004
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[PATCH] e1000 2/7: Workaround for link LED staying ON even when
parent
a5f4b1a7
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drivers/net/e1000/e1000_hw.h
drivers/net/e1000/e1000_hw.h
+9
-7
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drivers/net/e1000/e1000_hw.h
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b3a0f501
...
@@ -2019,7 +2019,7 @@ struct e1000_hw {
...
@@ -2019,7 +2019,7 @@ struct e1000_hw {
#define IGP01E1000_PSSR_MDIX_SHIFT 0x000B
/* shift right 11 */
#define IGP01E1000_PSSR_MDIX_SHIFT 0x000B
/* shift right 11 */
/* IGP01E1000 Specific Port Control Register - R/W */
/* IGP01E1000 Specific Port Control Register - R/W */
#define IGP01E1000_PSCR_TP_LOOPBACK 0x00
01
#define IGP01E1000_PSCR_TP_LOOPBACK 0x00
10
#define IGP01E1000_PSCR_CORRECT_NC_SCMBLR 0x0200
#define IGP01E1000_PSCR_CORRECT_NC_SCMBLR 0x0200
#define IGP01E1000_PSCR_TEN_CRS_SELECT 0x0400
#define IGP01E1000_PSCR_TEN_CRS_SELECT 0x0400
#define IGP01E1000_PSCR_FLIP_CHIP 0x0800
#define IGP01E1000_PSCR_FLIP_CHIP 0x0800
...
@@ -2029,16 +2029,18 @@ struct e1000_hw {
...
@@ -2029,16 +2029,18 @@ struct e1000_hw {
/* IGP01E1000 Specific Port Link Health Register */
/* IGP01E1000 Specific Port Link Health Register */
#define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000
#define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000
#define IGP01E1000_PLHR_GIG_SCRAMBLER_ERROR 0x4000
#define IGP01E1000_PLHR_GIG_SCRAMBLER_ERROR 0x4000
#define IGP01E1000_PLHR_MASTER_FAULT 0x2000
#define IGP01E1000_PLHR_MASTER_RESOLUTION 0x1000
#define IGP01E1000_PLHR_GIG_REM_RCVR_NOK 0x0800
/* LH */
#define IGP01E1000_PLHR_GIG_REM_RCVR_NOK 0x0800
/* LH */
#define IGP01E1000_PLHR_IDLE_ERROR_CNT_OFLOW 0x0400
/* LH */
#define IGP01E1000_PLHR_IDLE_ERROR_CNT_OFLOW 0x0400
/* LH */
#define IGP01E1000_PLHR_DATA_ERR_1 0x0200
/* LH */
#define IGP01E1000_PLHR_DATA_ERR_1 0x0200
/* LH */
#define IGP01E1000_PLHR_DATA_ERR_0 0x0100
#define IGP01E1000_PLHR_DATA_ERR_0 0x0100
#define IGP01E1000_PLHR_AUTONEG_FAULT 0x00
1
0
#define IGP01E1000_PLHR_AUTONEG_FAULT 0x00
4
0
#define IGP01E1000_PLHR_AUTONEG_ACTIVE 0x00
08
#define IGP01E1000_PLHR_AUTONEG_ACTIVE 0x00
10
#define IGP01E1000_PLHR_VALID_CHANNEL_D 0x000
4
#define IGP01E1000_PLHR_VALID_CHANNEL_D 0x000
8
#define IGP01E1000_PLHR_VALID_CHANNEL_C 0x000
2
#define IGP01E1000_PLHR_VALID_CHANNEL_C 0x000
4
#define IGP01E1000_PLHR_VALID_CHANNEL_B 0x000
1
#define IGP01E1000_PLHR_VALID_CHANNEL_B 0x000
2
#define IGP01E1000_PLHR_VALID_CHANNEL_A 0x000
0
#define IGP01E1000_PLHR_VALID_CHANNEL_A 0x000
1
/* IGP01E1000 Channel Quality Register */
/* IGP01E1000 Channel Quality Register */
#define IGP01E1000_MSE_CHANNEL_D 0x000F
#define IGP01E1000_MSE_CHANNEL_D 0x000F
...
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