Commit b4149dc7 authored by Yuval Mintz's avatar Yuval Mintz Committed by David S. Miller

qed: Print additional HW attention info

This patch utilizes the attention infrastructure to log additional
information that relates only to specific HW blocks.
For some of those HW blocks, it also stops automatically disabling the
attention generation as the attention is considered benign and thus
should only be logged; No fear of it flooding the system.
Signed-off-by: default avatarYuval Mintz <Yuval.Mintz@qlogic.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent ff38577a
This diff is collapsed.
...@@ -127,8 +127,20 @@ ...@@ -127,8 +127,20 @@
0x00c000UL 0x00c000UL
#define DORQ_REG_IFEN \ #define DORQ_REG_IFEN \
0x100040UL 0x100040UL
#define DORQ_REG_DB_DROP_REASON \
0x100a2cUL
#define DORQ_REG_DB_DROP_DETAILS \
0x100a24UL
#define DORQ_REG_DB_DROP_DETAILS_ADDRESS \
0x100a1cUL
#define GRC_REG_TIMEOUT_EN \ #define GRC_REG_TIMEOUT_EN \
0x050404UL 0x050404UL
#define GRC_REG_TIMEOUT_ATTN_ACCESS_VALID \
0x050054UL
#define GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_0 \
0x05004cUL
#define GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_1 \
0x050050UL
#define IGU_REG_BLOCK_CONFIGURATION \ #define IGU_REG_BLOCK_CONFIGURATION \
0x180040UL 0x180040UL
#define MCM_REG_INIT \ #define MCM_REG_INIT \
...@@ -155,6 +167,40 @@ ...@@ -155,6 +167,40 @@
0x1100000UL 0x1100000UL
#define PGLUE_B_REG_ADMIN_PER_PF_REGION \ #define PGLUE_B_REG_ADMIN_PER_PF_REGION \
0x2a9000UL 0x2a9000UL
#define PGLUE_B_REG_TX_ERR_WR_DETAILS2 \
0x2aa150UL
#define PGLUE_B_REG_TX_ERR_WR_ADD_31_0 \
0x2aa144UL
#define PGLUE_B_REG_TX_ERR_WR_ADD_63_32 \
0x2aa148UL
#define PGLUE_B_REG_TX_ERR_WR_DETAILS \
0x2aa14cUL
#define PGLUE_B_REG_TX_ERR_RD_ADD_31_0 \
0x2aa154UL
#define PGLUE_B_REG_TX_ERR_RD_ADD_63_32 \
0x2aa158UL
#define PGLUE_B_REG_TX_ERR_RD_DETAILS \
0x2aa15cUL
#define PGLUE_B_REG_TX_ERR_RD_DETAILS2 \
0x2aa160UL
#define PGLUE_B_REG_TX_ERR_WR_DETAILS_ICPL \
0x2aa164UL
#define PGLUE_B_REG_MASTER_ZLR_ERR_DETAILS \
0x2aa54cUL
#define PGLUE_B_REG_MASTER_ZLR_ERR_ADD_31_0 \
0x2aa544UL
#define PGLUE_B_REG_MASTER_ZLR_ERR_ADD_63_32 \
0x2aa548UL
#define PGLUE_B_REG_VF_ILT_ERR_ADD_31_0 \
0x2aae74UL
#define PGLUE_B_REG_VF_ILT_ERR_ADD_63_32 \
0x2aae78UL
#define PGLUE_B_REG_VF_ILT_ERR_DETAILS \
0x2aae7cUL
#define PGLUE_B_REG_VF_ILT_ERR_DETAILS2 \
0x2aae80UL
#define PGLUE_B_REG_LATCHED_ERRORS_CLR \
0x2aa3bcUL
#define PRM_REG_DISABLE_PRM \ #define PRM_REG_DISABLE_PRM \
0x230000UL 0x230000UL
#define PRS_REG_SOFT_RST \ #define PRS_REG_SOFT_RST \
...@@ -171,6 +217,14 @@ ...@@ -171,6 +217,14 @@
0x2a0040UL 0x2a0040UL
#define PSWHST2_REG_DBGSYN_ALMOST_FULL_THR \ #define PSWHST2_REG_DBGSYN_ALMOST_FULL_THR \
0x29e050UL 0x29e050UL
#define PSWHST_REG_INCORRECT_ACCESS_VALID \
0x2a0070UL
#define PSWHST_REG_INCORRECT_ACCESS_ADDRESS \
0x2a0074UL
#define PSWHST_REG_INCORRECT_ACCESS_DATA \
0x2a0068UL
#define PSWHST_REG_INCORRECT_ACCESS_LENGTH \
0x2a006cUL
#define PSWRD_REG_DBG_SELECT \ #define PSWRD_REG_DBG_SELECT \
0x29c040UL 0x29c040UL
#define PSWRD2_REG_CONF11 \ #define PSWRD2_REG_CONF11 \
...@@ -365,6 +419,10 @@ ...@@ -365,6 +419,10 @@
0x7 << 0) 0x7 << 0)
#define MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT \ #define MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT \
0 0
#define MCP_REG_CPU_STATE \
0xe05004UL
#define MCP_REG_CPU_EVENT_MASK \
0xe05008UL
#define PGLUE_B_REG_PF_BAR0_SIZE \ #define PGLUE_B_REG_PF_BAR0_SIZE \
0x2aae60UL 0x2aae60UL
#define PGLUE_B_REG_PF_BAR1_SIZE \ #define PGLUE_B_REG_PF_BAR1_SIZE \
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment