Commit b4ae3f22 authored by Jesse Barnes's avatar Jesse Barnes Committed by Daniel Vetter

drm/i915: load boot context at driver init time

According to the bspec for MBCTL:

Driver must set bit in the following scenarios:
  - to realod teh h/w boot context every time it gets loaded through OS
  - after an FLR clears the register (BIOS won't run afterwards)

References: https://bugs.freedesktop.org/show_bug.cgi?id=50237Signed-off-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: default avatarEugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 0f846f81
...@@ -3363,6 +3363,9 @@ static void gen6_init_clock_gating(struct drm_device *dev) ...@@ -3363,6 +3363,9 @@ static void gen6_init_clock_gating(struct drm_device *dev)
ILK_DPARB_CLK_GATE | ILK_DPARB_CLK_GATE |
ILK_DPFD_CLK_GATE); ILK_DPFD_CLK_GATE);
I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
GEN6_MBCTL_ENABLE_BOOT_FETCH);
for_each_pipe(pipe) { for_each_pipe(pipe) {
I915_WRITE(DSPCNTR(pipe), I915_WRITE(DSPCNTR(pipe),
I915_READ(DSPCNTR(pipe)) | I915_READ(DSPCNTR(pipe)) |
...@@ -3441,6 +3444,9 @@ static void ivybridge_init_clock_gating(struct drm_device *dev) ...@@ -3441,6 +3444,9 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
intel_flush_display_plane(dev_priv, pipe); intel_flush_display_plane(dev_priv, pipe);
} }
I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
GEN6_MBCTL_ENABLE_BOOT_FETCH);
gen7_setup_fixed_func_scheduler(dev_priv); gen7_setup_fixed_func_scheduler(dev_priv);
/* WaDisable4x2SubspanOptimization */ /* WaDisable4x2SubspanOptimization */
...@@ -3484,6 +3490,9 @@ static void valleyview_init_clock_gating(struct drm_device *dev) ...@@ -3484,6 +3490,9 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
GEN6_MBCTL_ENABLE_BOOT_FETCH);
/* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
* gating disable must be set. Failure to set it results in * gating disable must be set. Failure to set it results in
......
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