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Commit b53d3049 authored by James Zhu's avatar James Zhu Committed by Alex Deucher
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drm/amdgpu/vcn:Add new register offset/mask for VCN 

Add new register offset/mask for VCN to support
latest VCN implementation.
Signed-off-by: default avatarJames Zhu <James.Zhu@amd.com>
Acked-by: default avatarLeo Liu <leo.liu@amd.com>
Acked-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 8c6259be
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Showing with 32 additions and 0 deletions
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_offset.h
View file @ b53d3049
...@@ -82,6 +82,18 @@ ...@@ -82,6 +82,18 @@
#define mmUVD_LCM_CGC_CNTRL 0x0123 #define mmUVD_LCM_CGC_CNTRL 0x0123
#define mmUVD_LCM_CGC_CNTRL_BASE_IDX 1 #define mmUVD_LCM_CGC_CNTRL_BASE_IDX 1
#define mmUVD_MIF_CURR_UV_ADDR_CONFIG 0x0184
#define mmUVD_MIF_CURR_UV_ADDR_CONFIG_BASE_IDX 1
#define mmUVD_MIF_REF_UV_ADDR_CONFIG 0x0185
#define mmUVD_MIF_REF_UV_ADDR_CONFIG_BASE_IDX 1
#define mmUVD_MIF_RECON1_UV_ADDR_CONFIG 0x0186
#define mmUVD_MIF_RECON1_UV_ADDR_CONFIG_BASE_IDX 1
#define mmUVD_MIF_CURR_ADDR_CONFIG 0x0192
#define mmUVD_MIF_CURR_ADDR_CONFIG_BASE_IDX 1
#define mmUVD_MIF_REF_ADDR_CONFIG 0x0193
#define mmUVD_MIF_REF_ADDR_CONFIG_BASE_IDX 1
#define mmUVD_MIF_RECON1_ADDR_CONFIG 0x01c5
#define mmUVD_MIF_RECON1_ADDR_CONFIG_BASE_IDX 1
// addressBlock: uvd_uvdnpdec // addressBlock: uvd_uvdnpdec
// base address: 0x20000 // base address: 0x20000
...@@ -327,6 +339,8 @@ ...@@ -327,6 +339,8 @@
#define mmUVD_LMI_VM_CTRL_BASE_IDX 1 #define mmUVD_LMI_VM_CTRL_BASE_IDX 1
#define mmUVD_LMI_SWAP_CNTL 0x056d #define mmUVD_LMI_SWAP_CNTL 0x056d
#define mmUVD_LMI_SWAP_CNTL_BASE_IDX 1 #define mmUVD_LMI_SWAP_CNTL_BASE_IDX 1
#define mmUVD_MPC_CNTL 0x0577
#define mmUVD_MPC_CNTL_BASE_IDX 1
#define mmUVD_MPC_SET_MUXA0 0x0579 #define mmUVD_MPC_SET_MUXA0 0x0579
#define mmUVD_MPC_SET_MUXA0_BASE_IDX 1 #define mmUVD_MPC_SET_MUXA0_BASE_IDX 1
#define mmUVD_MPC_SET_MUXA1 0x057a #define mmUVD_MPC_SET_MUXA1 0x057a
......
drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_1_0_sh_mask.h
View file @ b53d3049
...@@ -985,6 +985,7 @@ ...@@ -985,6 +985,7 @@
#define UVD_LMI_CTRL2__STALL_ARB_UMC__SHIFT 0x8 #define UVD_LMI_CTRL2__STALL_ARB_UMC__SHIFT 0x8
#define UVD_LMI_CTRL2__MC_READ_ID_SEL__SHIFT 0x9 #define UVD_LMI_CTRL2__MC_READ_ID_SEL__SHIFT 0x9
#define UVD_LMI_CTRL2__MC_WRITE_ID_SEL__SHIFT 0xb #define UVD_LMI_CTRL2__MC_WRITE_ID_SEL__SHIFT 0xb
#define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT 0x11
#define UVD_LMI_CTRL2__SPH_DIS_MASK 0x00000001L #define UVD_LMI_CTRL2__SPH_DIS_MASK 0x00000001L
#define UVD_LMI_CTRL2__STALL_ARB_MASK 0x00000002L #define UVD_LMI_CTRL2__STALL_ARB_MASK 0x00000002L
#define UVD_LMI_CTRL2__ASSERT_UMC_URGENT_MASK 0x00000004L #define UVD_LMI_CTRL2__ASSERT_UMC_URGENT_MASK 0x00000004L
...@@ -993,6 +994,7 @@ ...@@ -993,6 +994,7 @@
#define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK 0x00000100L #define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK 0x00000100L
#define UVD_LMI_CTRL2__MC_READ_ID_SEL_MASK 0x00000600L #define UVD_LMI_CTRL2__MC_READ_ID_SEL_MASK 0x00000600L
#define UVD_LMI_CTRL2__MC_WRITE_ID_SEL_MASK 0x00001800L #define UVD_LMI_CTRL2__MC_WRITE_ID_SEL_MASK 0x00001800L
#define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM_MASK 0x01FE0000L
//UVD_MASTINT_EN //UVD_MASTINT_EN
#define UVD_MASTINT_EN__OVERRUN_RST__SHIFT 0x0 #define UVD_MASTINT_EN__OVERRUN_RST__SHIFT 0x0
#define UVD_MASTINT_EN__VCPU_EN__SHIFT 0x1 #define UVD_MASTINT_EN__VCPU_EN__SHIFT 0x1
...@@ -1045,6 +1047,19 @@ ...@@ -1045,6 +1047,19 @@
#define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN_MASK 0x01000000L #define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN_MASK 0x01000000L
#define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN_MASK 0x02000000L #define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN_MASK 0x02000000L
#define UVD_LMI_CTRL__RFU_MASK 0xF8000000L #define UVD_LMI_CTRL__RFU_MASK 0xF8000000L
//UVD_LMI_STATUS
#define UVD_LMI_STATUS__READ_CLEAN__SHIFT 0x0
#define UVD_LMI_STATUS__WRITE_CLEAN__SHIFT 0x1
#define UVD_LMI_STATUS__WRITE_CLEAN_RAW__SHIFT 0x2
#define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN__SHIFT 0x3
#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW__SHIFT 0x6
#define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW__SHIFT 0x9
#define UVD_LMI_STATUS__READ_CLEAN_MASK 0x00000001L
#define UVD_LMI_STATUS__WRITE_CLEAN_MASK 0x00000002L
#define UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK 0x00000004L
#define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK 0x00000008L
#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK 0x00000040L
#define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK 0x00000200L
//UVD_LMI_SWAP_CNTL //UVD_LMI_SWAP_CNTL
#define UVD_LMI_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x0 #define UVD_LMI_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x0
#define UVD_LMI_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2 #define UVD_LMI_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2
...@@ -1078,6 +1093,9 @@ ...@@ -1078,6 +1093,9 @@
#define UVD_LMI_SWAP_CNTL__RB_WR_MC_SWAP_MASK 0x0C000000L #define UVD_LMI_SWAP_CNTL__RB_WR_MC_SWAP_MASK 0x0C000000L
#define UVD_LMI_SWAP_CNTL__RE_MC_SWAP_MASK 0x30000000L #define UVD_LMI_SWAP_CNTL__RE_MC_SWAP_MASK 0x30000000L
#define UVD_LMI_SWAP_CNTL__MP_MC_SWAP_MASK 0xC0000000L #define UVD_LMI_SWAP_CNTL__MP_MC_SWAP_MASK 0xC0000000L
//UVD_MPC_CNTL
#define UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT 0x3
#define UVD_MPC_CNTL__REPLACEMENT_MODE_MASK 0x00000038L
//UVD_MPC_SET_MUXA0 //UVD_MPC_SET_MUXA0
#define UVD_MPC_SET_MUXA0__VARA_0__SHIFT 0x0 #define UVD_MPC_SET_MUXA0__VARA_0__SHIFT 0x0
#define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x6 #define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x6
......
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