Commit b5962294 authored by Horatiu Vultur's avatar Horatiu Vultur Committed by David S. Miller

net: mscc: ocelot: Add support for tcam

Add ACL support using the TCAM. Using ACL it is possible to create rules
in hardware to filter/redirect frames.
Signed-off-by: default avatarHoratiu Vultur <horatiu.vultur@microchip.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 6345266a
...@@ -132,11 +132,12 @@ switch@1010000 { ...@@ -132,11 +132,12 @@ switch@1010000 {
<0x1270000 0x100>, <0x1270000 0x100>,
<0x1280000 0x100>, <0x1280000 0x100>,
<0x1800000 0x80000>, <0x1800000 0x80000>,
<0x1880000 0x10000>; <0x1880000 0x10000>,
<0x1060000 0x10000>;
reg-names = "sys", "rew", "qs", "port0", "port1", reg-names = "sys", "rew", "qs", "port0", "port1",
"port2", "port3", "port4", "port5", "port6", "port2", "port3", "port4", "port5", "port6",
"port7", "port8", "port9", "port10", "qsys", "port7", "port8", "port9", "port10", "qsys",
"ana"; "ana", "s2";
interrupts = <21 22>; interrupts = <21 22>;
interrupt-names = "xtr", "inj"; interrupt-names = "xtr", "inj";
......
# SPDX-License-Identifier: (GPL-2.0 OR MIT) # SPDX-License-Identifier: (GPL-2.0 OR MIT)
obj-$(CONFIG_MSCC_OCELOT_SWITCH) += mscc_ocelot_common.o obj-$(CONFIG_MSCC_OCELOT_SWITCH) += mscc_ocelot_common.o
mscc_ocelot_common-y := ocelot.o ocelot_io.o mscc_ocelot_common-y := ocelot.o ocelot_io.o
mscc_ocelot_common-y += ocelot_regs.o ocelot_tc.o ocelot_police.o mscc_ocelot_common-y += ocelot_regs.o ocelot_tc.o ocelot_police.o ocelot_ace.o
obj-$(CONFIG_MSCC_OCELOT_SWITCH_OCELOT) += ocelot_board.o obj-$(CONFIG_MSCC_OCELOT_SWITCH_OCELOT) += ocelot_board.o
...@@ -22,6 +22,7 @@ ...@@ -22,6 +22,7 @@
#include <net/switchdev.h> #include <net/switchdev.h>
#include "ocelot.h" #include "ocelot.h"
#include "ocelot_ace.h"
#define TABLE_UPDATE_SLEEP_US 10 #define TABLE_UPDATE_SLEEP_US 10
#define TABLE_UPDATE_TIMEOUT_US 100000 #define TABLE_UPDATE_TIMEOUT_US 100000
...@@ -130,6 +131,13 @@ static void ocelot_mact_init(struct ocelot *ocelot) ...@@ -130,6 +131,13 @@ static void ocelot_mact_init(struct ocelot *ocelot)
ocelot_write(ocelot, MACACCESS_CMD_INIT, ANA_TABLES_MACACCESS); ocelot_write(ocelot, MACACCESS_CMD_INIT, ANA_TABLES_MACACCESS);
} }
static void ocelot_vcap_enable(struct ocelot *ocelot, struct ocelot_port *port)
{
ocelot_write_gix(ocelot, ANA_PORT_VCAP_S2_CFG_S2_ENA |
ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG(0xa),
ANA_PORT_VCAP_S2_CFG, port->chip_port);
}
static inline u32 ocelot_vlant_read_vlanaccess(struct ocelot *ocelot) static inline u32 ocelot_vlant_read_vlanaccess(struct ocelot *ocelot)
{ {
return ocelot_read(ocelot, ANA_TABLES_VLANACCESS); return ocelot_read(ocelot, ANA_TABLES_VLANACCESS);
...@@ -1662,6 +1670,9 @@ int ocelot_probe_port(struct ocelot *ocelot, u8 port, ...@@ -1662,6 +1670,9 @@ int ocelot_probe_port(struct ocelot *ocelot, u8 port,
/* Basic L2 initialization */ /* Basic L2 initialization */
ocelot_vlan_port_apply(ocelot, ocelot_port); ocelot_vlan_port_apply(ocelot, ocelot_port);
/* Enable vcap lookups */
ocelot_vcap_enable(ocelot, ocelot_port);
return 0; return 0;
err_register_netdev: err_register_netdev:
...@@ -1696,6 +1707,7 @@ int ocelot_init(struct ocelot *ocelot) ...@@ -1696,6 +1707,7 @@ int ocelot_init(struct ocelot *ocelot)
ocelot_mact_init(ocelot); ocelot_mact_init(ocelot);
ocelot_vlan_init(ocelot); ocelot_vlan_init(ocelot);
ocelot_ace_init(ocelot);
for (port = 0; port < ocelot->num_phys_ports; port++) { for (port = 0; port < ocelot->num_phys_ports; port++) {
/* Clear all counters (5 groups) */ /* Clear all counters (5 groups) */
...@@ -1808,6 +1820,7 @@ void ocelot_deinit(struct ocelot *ocelot) ...@@ -1808,6 +1820,7 @@ void ocelot_deinit(struct ocelot *ocelot)
{ {
destroy_workqueue(ocelot->stats_queue); destroy_workqueue(ocelot->stats_queue);
mutex_destroy(&ocelot->stats_lock); mutex_destroy(&ocelot->stats_lock);
ocelot_ace_deinit();
} }
EXPORT_SYMBOL(ocelot_deinit); EXPORT_SYMBOL(ocelot_deinit);
......
...@@ -69,6 +69,7 @@ enum ocelot_target { ...@@ -69,6 +69,7 @@ enum ocelot_target {
QSYS, QSYS,
REW, REW,
SYS, SYS,
S2,
HSIO, HSIO,
TARGET_MAX, TARGET_MAX,
}; };
...@@ -335,6 +336,13 @@ enum ocelot_reg { ...@@ -335,6 +336,13 @@ enum ocelot_reg {
SYS_CM_DATA_RD, SYS_CM_DATA_RD,
SYS_CM_OP, SYS_CM_OP,
SYS_CM_DATA, SYS_CM_DATA,
S2_CORE_UPDATE_CTRL = S2 << TARGET_OFFSET,
S2_CORE_MV_CFG,
S2_CACHE_ENTRY_DAT,
S2_CACHE_MASK_DAT,
S2_CACHE_ACTION_DAT,
S2_CACHE_CNT_DAT,
S2_CACHE_TG_DAT,
}; };
enum ocelot_regfield { enum ocelot_regfield {
......
This diff is collapsed.
/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
/* Microsemi Ocelot Switch driver
* Copyright (c) 2019 Microsemi Corporation
*/
#ifndef _MSCC_OCELOT_ACE_H_
#define _MSCC_OCELOT_ACE_H_
#include "ocelot.h"
#include <net/sch_generic.h>
#include <net/pkt_cls.h>
struct ocelot_ipv4 {
u8 addr[4];
};
enum ocelot_vcap_bit {
OCELOT_VCAP_BIT_ANY,
OCELOT_VCAP_BIT_0,
OCELOT_VCAP_BIT_1
};
struct ocelot_vcap_u8 {
u8 value[1];
u8 mask[1];
};
struct ocelot_vcap_u16 {
u8 value[2];
u8 mask[2];
};
struct ocelot_vcap_u24 {
u8 value[3];
u8 mask[3];
};
struct ocelot_vcap_u32 {
u8 value[4];
u8 mask[4];
};
struct ocelot_vcap_u40 {
u8 value[5];
u8 mask[5];
};
struct ocelot_vcap_u48 {
u8 value[6];
u8 mask[6];
};
struct ocelot_vcap_u64 {
u8 value[8];
u8 mask[8];
};
struct ocelot_vcap_u128 {
u8 value[16];
u8 mask[16];
};
struct ocelot_vcap_vid {
u16 value;
u16 mask;
};
struct ocelot_vcap_ipv4 {
struct ocelot_ipv4 value;
struct ocelot_ipv4 mask;
};
struct ocelot_vcap_udp_tcp {
u16 value;
u16 mask;
};
enum ocelot_ace_type {
OCELOT_ACE_TYPE_ANY,
OCELOT_ACE_TYPE_ETYPE,
OCELOT_ACE_TYPE_LLC,
OCELOT_ACE_TYPE_SNAP,
OCELOT_ACE_TYPE_ARP,
OCELOT_ACE_TYPE_IPV4,
OCELOT_ACE_TYPE_IPV6
};
struct ocelot_ace_vlan {
struct ocelot_vcap_vid vid; /* VLAN ID (12 bit) */
struct ocelot_vcap_u8 pcp; /* PCP (3 bit) */
enum ocelot_vcap_bit dei; /* DEI */
enum ocelot_vcap_bit tagged; /* Tagged/untagged frame */
};
struct ocelot_ace_frame_etype {
struct ocelot_vcap_u48 dmac;
struct ocelot_vcap_u48 smac;
struct ocelot_vcap_u16 etype;
struct ocelot_vcap_u16 data; /* MAC data */
};
struct ocelot_ace_frame_llc {
struct ocelot_vcap_u48 dmac;
struct ocelot_vcap_u48 smac;
/* LLC header: DSAP at byte 0, SSAP at byte 1, Control at byte 2 */
struct ocelot_vcap_u32 llc;
};
struct ocelot_ace_frame_snap {
struct ocelot_vcap_u48 dmac;
struct ocelot_vcap_u48 smac;
/* SNAP header: Organization Code at byte 0, Type at byte 3 */
struct ocelot_vcap_u40 snap;
};
struct ocelot_ace_frame_arp {
struct ocelot_vcap_u48 smac;
enum ocelot_vcap_bit arp; /* Opcode ARP/RARP */
enum ocelot_vcap_bit req; /* Opcode request/reply */
enum ocelot_vcap_bit unknown; /* Opcode unknown */
enum ocelot_vcap_bit smac_match; /* Sender MAC matches SMAC */
enum ocelot_vcap_bit dmac_match; /* Target MAC matches DMAC */
/**< Protocol addr. length 4, hardware length 6 */
enum ocelot_vcap_bit length;
enum ocelot_vcap_bit ip; /* Protocol address type IP */
enum ocelot_vcap_bit ethernet; /* Hardware address type Ethernet */
struct ocelot_vcap_ipv4 sip; /* Sender IP address */
struct ocelot_vcap_ipv4 dip; /* Target IP address */
};
struct ocelot_ace_frame_ipv4 {
enum ocelot_vcap_bit ttl; /* TTL zero */
enum ocelot_vcap_bit fragment; /* Fragment */
enum ocelot_vcap_bit options; /* Header options */
struct ocelot_vcap_u8 ds;
struct ocelot_vcap_u8 proto; /* Protocol */
struct ocelot_vcap_ipv4 sip; /* Source IP address */
struct ocelot_vcap_ipv4 dip; /* Destination IP address */
struct ocelot_vcap_u48 data; /* Not UDP/TCP: IP data */
struct ocelot_vcap_udp_tcp sport; /* UDP/TCP: Source port */
struct ocelot_vcap_udp_tcp dport; /* UDP/TCP: Destination port */
enum ocelot_vcap_bit tcp_fin;
enum ocelot_vcap_bit tcp_syn;
enum ocelot_vcap_bit tcp_rst;
enum ocelot_vcap_bit tcp_psh;
enum ocelot_vcap_bit tcp_ack;
enum ocelot_vcap_bit tcp_urg;
enum ocelot_vcap_bit sip_eq_dip; /* SIP equals DIP */
enum ocelot_vcap_bit sport_eq_dport; /* SPORT equals DPORT */
enum ocelot_vcap_bit seq_zero; /* TCP sequence number is zero */
};
struct ocelot_ace_frame_ipv6 {
struct ocelot_vcap_u8 proto; /* IPv6 protocol */
struct ocelot_vcap_u128 sip; /* IPv6 source (byte 0-7 ignored) */
enum ocelot_vcap_bit ttl; /* TTL zero */
struct ocelot_vcap_u8 ds;
struct ocelot_vcap_u48 data; /* Not UDP/TCP: IP data */
struct ocelot_vcap_udp_tcp sport;
struct ocelot_vcap_udp_tcp dport;
enum ocelot_vcap_bit tcp_fin;
enum ocelot_vcap_bit tcp_syn;
enum ocelot_vcap_bit tcp_rst;
enum ocelot_vcap_bit tcp_psh;
enum ocelot_vcap_bit tcp_ack;
enum ocelot_vcap_bit tcp_urg;
enum ocelot_vcap_bit sip_eq_dip; /* SIP equals DIP */
enum ocelot_vcap_bit sport_eq_dport; /* SPORT equals DPORT */
enum ocelot_vcap_bit seq_zero; /* TCP sequence number is zero */
};
enum ocelot_ace_action {
OCELOT_ACL_ACTION_DROP,
OCELOT_ACL_ACTION_TRAP,
};
struct ocelot_ace_stats {
u64 bytes;
u64 pkts;
u64 used;
};
struct ocelot_ace_rule {
struct list_head list;
struct ocelot_port *port;
u16 prio;
u32 id;
enum ocelot_ace_action action;
struct ocelot_ace_stats stats;
int chip_port;
enum ocelot_vcap_bit dmac_mc;
enum ocelot_vcap_bit dmac_bc;
struct ocelot_ace_vlan vlan;
enum ocelot_ace_type type;
union {
/* ocelot_ACE_TYPE_ANY: No specific fields */
struct ocelot_ace_frame_etype etype;
struct ocelot_ace_frame_llc llc;
struct ocelot_ace_frame_snap snap;
struct ocelot_ace_frame_arp arp;
struct ocelot_ace_frame_ipv4 ipv4;
struct ocelot_ace_frame_ipv6 ipv6;
} frame;
};
struct ocelot_acl_block {
struct list_head rules;
struct ocelot *ocelot;
int count;
};
int ocelot_ace_rule_offload_add(struct ocelot_ace_rule *rule);
int ocelot_ace_rule_offload_del(struct ocelot_ace_rule *rule);
int ocelot_ace_rule_stats_update(struct ocelot_ace_rule *rule);
int ocelot_ace_init(struct ocelot *ocelot);
void ocelot_ace_deinit(void);
#endif /* _MSCC_OCELOT_ACE_H_ */
...@@ -188,6 +188,7 @@ static int mscc_ocelot_probe(struct platform_device *pdev) ...@@ -188,6 +188,7 @@ static int mscc_ocelot_probe(struct platform_device *pdev)
{ QSYS, "qsys" }, { QSYS, "qsys" },
{ ANA, "ana" }, { ANA, "ana" },
{ QS, "qs" }, { QS, "qs" },
{ S2, "s2" },
}; };
if (!np && !pdev->dev.platform_data) if (!np && !pdev->dev.platform_data)
......
...@@ -224,12 +224,23 @@ static const u32 ocelot_sys_regmap[] = { ...@@ -224,12 +224,23 @@ static const u32 ocelot_sys_regmap[] = {
REG(SYS_PTP_CFG, 0x0006c4), REG(SYS_PTP_CFG, 0x0006c4),
}; };
static const u32 ocelot_s2_regmap[] = {
REG(S2_CORE_UPDATE_CTRL, 0x000000),
REG(S2_CORE_MV_CFG, 0x000004),
REG(S2_CACHE_ENTRY_DAT, 0x000008),
REG(S2_CACHE_MASK_DAT, 0x000108),
REG(S2_CACHE_ACTION_DAT, 0x000208),
REG(S2_CACHE_CNT_DAT, 0x000308),
REG(S2_CACHE_TG_DAT, 0x000388),
};
static const u32 *ocelot_regmap[] = { static const u32 *ocelot_regmap[] = {
[ANA] = ocelot_ana_regmap, [ANA] = ocelot_ana_regmap,
[QS] = ocelot_qs_regmap, [QS] = ocelot_qs_regmap,
[QSYS] = ocelot_qsys_regmap, [QSYS] = ocelot_qsys_regmap,
[REW] = ocelot_rew_regmap, [REW] = ocelot_rew_regmap,
[SYS] = ocelot_sys_regmap, [SYS] = ocelot_sys_regmap,
[S2] = ocelot_s2_regmap,
}; };
static const struct reg_field ocelot_regfields[] = { static const struct reg_field ocelot_regfields[] = {
......
/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
/* Microsemi Ocelot Switch driver
* Copyright (c) 2018 Microsemi Corporation
*/
#ifndef _OCELOT_S2_CORE_H_
#define _OCELOT_S2_CORE_H_
#define S2_CORE_UPDATE_CTRL_UPDATE_CMD(x) (((x) << 22) & GENMASK(24, 22))
#define S2_CORE_UPDATE_CTRL_UPDATE_CMD_M GENMASK(24, 22)
#define S2_CORE_UPDATE_CTRL_UPDATE_CMD_X(x) (((x) & GENMASK(24, 22)) >> 22)
#define S2_CORE_UPDATE_CTRL_UPDATE_ENTRY_DIS BIT(21)
#define S2_CORE_UPDATE_CTRL_UPDATE_ACTION_DIS BIT(20)
#define S2_CORE_UPDATE_CTRL_UPDATE_CNT_DIS BIT(19)
#define S2_CORE_UPDATE_CTRL_UPDATE_ADDR(x) (((x) << 3) & GENMASK(18, 3))
#define S2_CORE_UPDATE_CTRL_UPDATE_ADDR_M GENMASK(18, 3)
#define S2_CORE_UPDATE_CTRL_UPDATE_ADDR_X(x) (((x) & GENMASK(18, 3)) >> 3)
#define S2_CORE_UPDATE_CTRL_UPDATE_SHOT BIT(2)
#define S2_CORE_UPDATE_CTRL_CLEAR_CACHE BIT(1)
#define S2_CORE_UPDATE_CTRL_MV_TRAFFIC_IGN BIT(0)
#define S2_CORE_MV_CFG_MV_NUM_POS(x) (((x) << 16) & GENMASK(31, 16))
#define S2_CORE_MV_CFG_MV_NUM_POS_M GENMASK(31, 16)
#define S2_CORE_MV_CFG_MV_NUM_POS_X(x) (((x) & GENMASK(31, 16)) >> 16)
#define S2_CORE_MV_CFG_MV_SIZE(x) ((x) & GENMASK(15, 0))
#define S2_CORE_MV_CFG_MV_SIZE_M GENMASK(15, 0)
#define S2_CACHE_ENTRY_DAT_RSZ 0x4
#define S2_CACHE_MASK_DAT_RSZ 0x4
#define S2_CACHE_ACTION_DAT_RSZ 0x4
#define S2_CACHE_CNT_DAT_RSZ 0x4
#define S2_STICKY_VCAP_ROW_DELETED_STICKY BIT(0)
#define S2_BIST_CTRL_TCAM_BIST BIT(1)
#define S2_BIST_CTRL_TCAM_INIT BIT(0)
#define S2_BIST_CFG_TCAM_BIST_SOE_ENA BIT(8)
#define S2_BIST_CFG_TCAM_HCG_DIS BIT(7)
#define S2_BIST_CFG_TCAM_CG_DIS BIT(6)
#define S2_BIST_CFG_TCAM_BIAS(x) ((x) & GENMASK(5, 0))
#define S2_BIST_CFG_TCAM_BIAS_M GENMASK(5, 0)
#define S2_BIST_STAT_BIST_RT_ERR BIT(15)
#define S2_BIST_STAT_BIST_PENC_ERR BIT(14)
#define S2_BIST_STAT_BIST_COMP_ERR BIT(13)
#define S2_BIST_STAT_BIST_ADDR_ERR BIT(12)
#define S2_BIST_STAT_BIST_BL1E_ERR BIT(11)
#define S2_BIST_STAT_BIST_BL1_ERR BIT(10)
#define S2_BIST_STAT_BIST_BL0E_ERR BIT(9)
#define S2_BIST_STAT_BIST_BL0_ERR BIT(8)
#define S2_BIST_STAT_BIST_PH1_ERR BIT(7)
#define S2_BIST_STAT_BIST_PH0_ERR BIT(6)
#define S2_BIST_STAT_BIST_PV1_ERR BIT(5)
#define S2_BIST_STAT_BIST_PV0_ERR BIT(4)
#define S2_BIST_STAT_BIST_RUN BIT(3)
#define S2_BIST_STAT_BIST_ERR BIT(2)
#define S2_BIST_STAT_BIST_BUSY BIT(1)
#define S2_BIST_STAT_TCAM_RDY BIT(0)
#endif /* _OCELOT_S2_CORE_H_ */
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