Commit b5ad2c21 authored by Markos Chandras's avatar Markos Chandras

MIPS: mm: scache: Add secondary cache support for MIPS R6 cores

The secondary cache initialization and configuration code is processor
specific so we need to handle MIPS R6 cores as well.
Signed-off-by: default avatarMarkos Chandras <markos.chandras@imgtec.com>
parent 4ee48627
...@@ -1473,7 +1473,8 @@ static void setup_scache(void) ...@@ -1473,7 +1473,8 @@ static void setup_scache(void)
default: default:
if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 | if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)) { MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R1 |
MIPS_CPU_ISA_M64R2 | MIPS_CPU_ISA_M64R6)) {
#ifdef CONFIG_MIPS_CPU_SCACHE #ifdef CONFIG_MIPS_CPU_SCACHE
if (mips_sc_init ()) { if (mips_sc_init ()) {
scache_size = c->scache.ways * c->scache.sets * c->scache.linesz; scache_size = c->scache.ways * c->scache.sets * c->scache.linesz;
......
...@@ -105,7 +105,8 @@ static inline int __init mips_sc_probe(void) ...@@ -105,7 +105,8 @@ static inline int __init mips_sc_probe(void)
/* Ignore anything but MIPSxx processors */ /* Ignore anything but MIPSxx processors */
if (!(c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 | if (!(c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2))) MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R1 |
MIPS_CPU_ISA_M64R2 | MIPS_CPU_ISA_M64R6)))
return 0; return 0;
/* Does this MIPS32/MIPS64 CPU have a config2 register? */ /* Does this MIPS32/MIPS64 CPU have a config2 register? */
......
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