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Commit b61c4ff9 authored by Michal Simek's avatar Michal Simek
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arm64: zynqmp: Enable xlnx,zynqmp-dwc3 driver for xilinx boards 

The commit 84770f02 ("usb: dwc3: Add driver for Xilinx platforms")
finally add proper support for Xilinx dwc3 driver. This patch is adding DT
description for it.
Signed-off-by: default avatarMichal Simek <michal.simek@xilinx.com>
Reviewed-by: default avatarMichael Tretter <m.tretter@pengutronix.de>
Link: https://lore.kernel.org/r/640a3bc0dc3e32560d3e84c2f78b5ae561396eb0.1628244703.git.michal.simek@xilinx.com
parent 9d648af4
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Showing with 122 additions and 21 deletions
arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts
View file @ b61c4ff9
......@@ -27,6 +27,7 @@ aliases {
rtc0 = &rtc;
serial0 = &uart0;
spi0 = &qspi;
usb0 = &usb0;
};
chosen {
......@@ -404,9 +405,14 @@ &usb0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0_default>;
dr_mode = "host";
phy-names = "usb3-phy";
phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
};
&dwc3_0 {
status = "okay";
dr_mode = "host";
snps,usb3_lpm_capable;
maximum-speed = "super-speed";
};
......
arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts
View file @ b61c4ff9
......@@ -26,6 +26,7 @@ aliases {
serial1 = &uart1;
spi0 = &spi0;
spi1 = &spi1;
usb0 = &usb1;
};
chosen {
......@@ -479,7 +480,13 @@ &usb1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb1_default>;
};
&dwc3_1 {
status = "okay";
dr_mode = "host";
snps,usb3_lpm_capable;
maximum-speed = "super-speed";
};
&uart0 {
......
arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts
View file @ b61c4ff9
......@@ -24,6 +24,8 @@ aliases {
rtc0 = &rtc;
serial0 = &uart0;
serial1 = &uart1;
usb0 = &usb0;
usb1 = &usb1;
};
chosen {
......@@ -147,11 +149,23 @@ &uart1 {
&usb0 {
status = "okay";
};
&dwc3_0 {
status = "okay";
dr_mode = "host";
snps,usb3_lpm_capable;
maximum-speed = "super-speed";
};
/* ULPI SMSC USB3320 */
&usb1 {
status = "okay";
};
&dwc3_1 {
status = "okay";
dr_mode = "host";
snps,usb3_lpm_capable;
maximum-speed = "super-speed";
};
arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
View file @ b61c4ff9
......@@ -30,6 +30,8 @@ aliases {
serial2 = &dcc;
spi0 = &spi0;
spi1 = &spi1;
usb0 = &usb0;
usb1 = &usb1;
mmc0 = &sdhci0;
mmc1 = &sdhci1;
};
......@@ -537,9 +539,13 @@ &usb0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0_default>;
dr_mode = "peripheral";
phy-names = "usb3-phy";
phys = <&psgtr 2 PHY_TYPE_USB3 0 0>;
};
&dwc3_0 {
status = "okay";
dr_mode = "peripheral";
maximum-speed = "super-speed";
};
......@@ -548,9 +554,13 @@ &usb1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb1_default>;
dr_mode = "host";
phy-names = "usb3-phy";
phys = <&psgtr 3 PHY_TYPE_USB3 1 0>;
};
&dwc3_1 {
status = "okay";
dr_mode = "host";
maximum-speed = "super-speed";
};
......
arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
View file @ b61c4ff9
......@@ -31,6 +31,7 @@ aliases {
serial1 = &uart1;
serial2 = &dcc;
spi0 = &qspi;
usb0 = &usb0;
};
chosen {
......@@ -997,9 +998,14 @@ &usb0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0_default>;
dr_mode = "host";
phy-names = "usb3-phy";
phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
};
&dwc3_0 {
status = "okay";
dr_mode = "host";
snps,usb3_lpm_capable;
maximum-speed = "super-speed";
};
......
arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts
View file @ b61c4ff9
......@@ -29,6 +29,7 @@ aliases {
serial1 = &uart1;
serial2 = &dcc;
spi0 = &qspi;
usb0 = &usb0;
};
chosen {
......@@ -481,9 +482,14 @@ &usb0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0_default>;
dr_mode = "host";
phy-names = "usb3-phy";
phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
};
&dwc3_0 {
status = "okay";
dr_mode = "host";
snps,usb3_lpm_capable;
maximum-speed = "super-speed";
};
......
arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts
View file @ b61c4ff9
......@@ -29,6 +29,7 @@ aliases {
serial1 = &uart1;
serial2 = &dcc;
spi0 = &qspi;
usb0 = &usb0;
};
chosen {
......@@ -493,9 +494,14 @@ &usb0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0_default>;
dr_mode = "host";
phy-names = "usb3-phy";
phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
};
&dwc3_0 {
status = "okay";
dr_mode = "host";
snps,usb3_lpm_capable;
maximum-speed = "super-speed";
};
......
arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts
View file @ b61c4ff9
......@@ -31,6 +31,7 @@ aliases {
serial1 = &uart1;
serial2 = &dcc;
spi0 = &qspi;
usb0 = &usb0;
};
chosen {
......@@ -990,9 +991,14 @@ &usb0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0_default>;
dr_mode = "host";
phy-names = "usb3-phy";
phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
};
&dwc3_0 {
status = "okay";
dr_mode = "host";
snps,usb3_lpm_capable;
maximum-speed = "super-speed";
};
......
arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts
View file @ b61c4ff9
......@@ -30,6 +30,7 @@ aliases {
serial0 = &uart0;
serial1 = &dcc;
spi0 = &qspi;
usb0 = &usb0;
};
chosen {
......@@ -827,9 +828,14 @@ &usb0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0_default>;
dr_mode = "host";
phy-names = "usb3-phy";
phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
};
&dwc3_0 {
status = "okay";
dr_mode = "host";
snps,usb3_lpm_capable;
maximum-speed = "super-speed";
};
......
arch/arm64/boot/dts/xilinx/zynqmp.dtsi
View file @ b61c4ff9
......@@ -2,7 +2,7 @@
/*
* dts file for Xilinx ZynqMP
*
* (C) Copyright 2014 - 2019, Xilinx, Inc.
* (C) Copyright 2014 - 2021, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*
......@@ -805,24 +805,58 @@ uart1: serial@ff010000 {
power-domains = <&zynqmp_firmware PD_UART_1>;
};
usb0: usb@fe200000 {
compatible = "snps,dwc3";
usb0: usb@ff9d0000 {
#address-cells = <2>;
#size-cells = <2>;
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 65 4>;
reg = <0x0 0xfe200000 0x0 0x40000>;
clock-names = "clk_xin", "clk_ahb";
compatible = "xlnx,zynqmp-dwc3";
reg = <0x0 0xff9d0000 0x0 0x100>;
clock-names = "bus_clk", "ref_clk";
power-domains = <&zynqmp_firmware PD_USB_0>;
resets = <&zynqmp_reset ZYNQMP_RESET_USB0_CORERESET>,
<&zynqmp_reset ZYNQMP_RESET_USB0_HIBERRESET>,
<&zynqmp_reset ZYNQMP_RESET_USB0_APB>;
reset-names = "usb_crst", "usb_hibrst", "usb_apbrst";
ranges;
dwc3_0: usb@fe200000 {
compatible = "snps,dwc3";
reg = <0x0 0xfe200000 0x0 0x40000>;
interrupt-parent = <&gic>;
interrupt-names = "dwc_usb3", "otg";
interrupts = <0 65 4>, <0 69 4>;
#stream-id-cells = <1>;
iommus = <&smmu 0x860>;
snps,quirk-frame-length-adjustment = <0x20>;
/* dma-coherent; */
};
};
usb1: usb@fe300000 {
compatible = "snps,dwc3";
usb1: usb@ff9e0000 {
#address-cells = <2>;
#size-cells = <2>;
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 70 4>;
reg = <0x0 0xfe300000 0x0 0x40000>;
clock-names = "clk_xin", "clk_ahb";
compatible = "xlnx,zynqmp-dwc3";
reg = <0x0 0xff9e0000 0x0 0x100>;
clock-names = "bus_clk", "ref_clk";
power-domains = <&zynqmp_firmware PD_USB_1>;
resets = <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>,
<&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>,
<&zynqmp_reset ZYNQMP_RESET_USB1_APB>;
reset-names = "usb_crst", "usb_hibrst", "usb_apbrst";
ranges;
dwc3_1: usb@fe300000 {
compatible = "snps,dwc3";
reg = <0x0 0xfe300000 0x0 0x40000>;
interrupt-parent = <&gic>;
interrupt-names = "dwc_usb3", "otg";
interrupts = <0 70 4>, <0 74 4>;
#stream-id-cells = <1>;
iommus = <&smmu 0x861>;
snps,quirk-frame-length-adjustment = <0x20>;
/* dma-coherent; */
};
};
watchdog0: watchdog@fd4d0000 {
......
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