Commit b63bebe2 authored by Vladimir Murzin's avatar Vladimir Murzin Committed by Christoffer Dall

arm64: KVM: remove misleading comment on pmu status

Comment about how PMU access is handled is not relavant since v4.6
where proper PMU support was added in.
Signed-off-by: default avatarVladimir Murzin <vladimir.murzin@arm.com>
Acked-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
Signed-off-by: default avatarChristoffer Dall <christoffer.dall@linaro.org>
parent cabdc5c5
...@@ -823,14 +823,6 @@ static bool access_pmuserenr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, ...@@ -823,14 +823,6 @@ static bool access_pmuserenr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
* Architected system registers. * Architected system registers.
* Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2 * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2
* *
* We could trap ID_DFR0 and tell the guest we don't support performance
* monitoring. Unfortunately the patch to make the kernel check ID_DFR0 was
* NAKed, so it will read the PMCR anyway.
*
* Therefore we tell the guest we have 0 counters. Unfortunately, we
* must always support PMCCNTR (the cycle counter): we just RAZ/WI for
* all PM registers, which doesn't crash the guest kernel at least.
*
* Debug handling: We do trap most, if not all debug related system * Debug handling: We do trap most, if not all debug related system
* registers. The implementation is good enough to ensure that a guest * registers. The implementation is good enough to ensure that a guest
* can use these with minimal performance degradation. The drawback is * can use these with minimal performance degradation. The drawback is
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