Commit b6e65d18 authored by Ping-Ke Shih's avatar Ping-Ke Shih Committed by Kalle Valo

wifi: rtw89: mac: return held quota of DLE when changing MAC-1

DLE (data link engine) could hold quota when we are going to enable/disable
MAC-1 block, so trigger hardware to return all held quota.
Signed-off-by: default avatarPing-Ke Shih <pkshih@realtek.com>
Signed-off-by: default avatarKalle Valo <kvalo@kernel.org>
Link: https://msgid.link/20240209065229.34515-4-pkshih@realtek.com
parent e10cd2dd
......@@ -3192,13 +3192,11 @@ static int set_cpuio_ax(struct rtw89_dev *rtwdev,
return 0;
}
int rtw89_mac_dle_quota_change(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode)
int rtw89_mac_dle_quota_change(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode,
bool band1_en)
{
const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
const struct rtw89_dle_mem *cfg;
struct rtw89_cpuio_ctrl ctrl_para = {0};
u16 pkt_id;
int ret;
cfg = get_dle_mem_cfg(rtwdev, mode);
if (!cfg) {
......@@ -3213,6 +3211,16 @@ int rtw89_mac_dle_quota_change(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mod
dle_quota_cfg(rtwdev, cfg, INVALID_QT_WCPU);
return mac->dle_quota_change(rtwdev, band1_en);
}
static int dle_quota_change_ax(struct rtw89_dev *rtwdev, bool band1_en)
{
const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
struct rtw89_cpuio_ctrl ctrl_para = {0};
u16 pkt_id;
int ret;
ret = mac->dle_buf_req(rtwdev, 0x20, true, &pkt_id);
if (ret) {
rtw89_err(rtwdev, "[ERR]WDE DLE buf req\n");
......@@ -3301,7 +3309,7 @@ static int band1_enable_ax(struct rtw89_dev *rtwdev)
return ret;
}
ret = rtw89_mac_dle_quota_change(rtwdev, rtwdev->mac.qta_mode);
ret = rtw89_mac_dle_quota_change(rtwdev, rtwdev->mac.qta_mode, true);
if (ret) {
rtw89_err(rtwdev, "[ERR]DLE quota change %d\n", ret);
return ret;
......@@ -6218,6 +6226,7 @@ const struct rtw89_mac_gen_def rtw89_mac_gen_ax = {
.wde_quota_cfg = wde_quota_cfg_ax,
.ple_quota_cfg = ple_quota_cfg_ax,
.set_cpuio = set_cpuio_ax,
.dle_quota_change = dle_quota_change_ax,
.disable_cpu = rtw89_mac_disable_cpu_ax,
.fwdl_enable_wcpu = rtw89_mac_enable_cpu_ax,
......
......@@ -932,6 +932,7 @@ struct rtw89_mac_gen_def {
const struct rtw89_ple_quota *max_cfg);
int (*set_cpuio)(struct rtw89_dev *rtwdev,
struct rtw89_cpuio_ctrl *ctrl_para, bool wd);
int (*dle_quota_change)(struct rtw89_dev *rtwdev, bool band1_en);
void (*disable_cpu)(struct rtw89_dev *rtwdev);
int (*fwdl_enable_wcpu)(struct rtw89_dev *rtwdev, u8 boot_reason,
......@@ -1388,7 +1389,8 @@ int rtw89_mac_resize_ple_rx_quota(struct rtw89_dev *rtwdev, bool wow);
int rtw89_mac_ptk_drop_by_band_and_wait(struct rtw89_dev *rtwdev,
enum rtw89_mac_idx band);
void rtw89_mac_hw_mgnt_sec(struct rtw89_dev *rtwdev, bool wow);
int rtw89_mac_dle_quota_change(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode);
int rtw89_mac_dle_quota_change(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode,
bool band1_en);
int rtw89_mac_get_dle_rsvd_qt_cfg(struct rtw89_dev *rtwdev,
enum rtw89_mac_dle_rsvd_qt_type type,
struct rtw89_mac_dle_rsvd_qt_cfg *cfg);
......
......@@ -1449,6 +1449,71 @@ static int set_cpuio_be(struct rtw89_dev *rtwdev,
return 0;
}
static int dle_upd_qta_aval_page_be(struct rtw89_dev *rtwdev,
enum rtw89_mac_dle_ctrl_type type,
enum rtw89_mac_dle_ple_quota_id quota_id)
{
u32 val;
if (type == DLE_CTRL_TYPE_WDE) {
rtw89_write32_mask(rtwdev, R_BE_WDE_BUFMGN_CTL,
B_BE_WDE_AVAL_UPD_QTAID_MASK, quota_id);
rtw89_write32_set(rtwdev, R_BE_WDE_BUFMGN_CTL, B_BE_WDE_AVAL_UPD_REQ);
return read_poll_timeout(rtw89_read32, val,
!(val & B_BE_WDE_AVAL_UPD_REQ),
1, 2000, false, rtwdev, R_BE_WDE_BUFMGN_CTL);
} else if (type == DLE_CTRL_TYPE_PLE) {
rtw89_write32_mask(rtwdev, R_BE_PLE_BUFMGN_CTL,
B_BE_PLE_AVAL_UPD_QTAID_MASK, quota_id);
rtw89_write32_set(rtwdev, R_BE_PLE_BUFMGN_CTL, B_BE_PLE_AVAL_UPD_REQ);
return read_poll_timeout(rtw89_read32, val,
!(val & B_BE_PLE_AVAL_UPD_REQ),
1, 2000, false, rtwdev, R_BE_PLE_BUFMGN_CTL);
}
rtw89_warn(rtwdev, "%s wrong type %d\n", __func__, type);
return -EINVAL;
}
static int dle_quota_change_be(struct rtw89_dev *rtwdev, bool band1_en)
{
int ret;
if (band1_en) {
ret = dle_upd_qta_aval_page_be(rtwdev, DLE_CTRL_TYPE_PLE,
PLE_QTAID_B0_TXPL);
if (ret) {
rtw89_err(rtwdev, "update PLE B0 TX avail page fail %d\n", ret);
return ret;
}
ret = dle_upd_qta_aval_page_be(rtwdev, DLE_CTRL_TYPE_PLE,
PLE_QTAID_CMAC0_RX);
if (ret) {
rtw89_err(rtwdev, "update PLE CMAC0 RX avail page fail %d\n", ret);
return ret;
}
} else {
ret = dle_upd_qta_aval_page_be(rtwdev, DLE_CTRL_TYPE_PLE,
PLE_QTAID_B1_TXPL);
if (ret) {
rtw89_err(rtwdev, "update PLE B1 TX avail page fail %d\n", ret);
return ret;
}
ret = dle_upd_qta_aval_page_be(rtwdev, DLE_CTRL_TYPE_PLE,
PLE_QTAID_CMAC1_RX);
if (ret) {
rtw89_err(rtwdev, "update PLE CMAC1 RX avail page fail %d\n", ret);
return ret;
}
}
return 0;
}
static int preload_init_be(struct rtw89_dev *rtwdev, u8 mac_idx,
enum rtw89_qta_mode mode)
{
......@@ -1538,7 +1603,7 @@ static int band1_enable_be(struct rtw89_dev *rtwdev)
return ret;
}
ret = rtw89_mac_dle_quota_change(rtwdev, rtwdev->mac.qta_mode);
ret = rtw89_mac_dle_quota_change(rtwdev, rtwdev->mac.qta_mode, true);
if (ret) {
rtw89_err(rtwdev, "[ERR]DLE quota change %d\n", ret);
return ret;
......@@ -1593,7 +1658,7 @@ static int band1_disable_be(struct rtw89_dev *rtwdev)
return ret;
}
ret = rtw89_mac_dle_quota_change(rtwdev, rtwdev->mac.qta_mode);
ret = rtw89_mac_dle_quota_change(rtwdev, rtwdev->mac.qta_mode, false);
if (ret) {
rtw89_err(rtwdev, "[ERR]DLE quota change %d\n", ret);
return ret;
......@@ -2347,6 +2412,7 @@ const struct rtw89_mac_gen_def rtw89_mac_gen_be = {
.wde_quota_cfg = wde_quota_cfg_be,
.ple_quota_cfg = ple_quota_cfg_be,
.set_cpuio = set_cpuio_be,
.dle_quota_change = dle_quota_change_be,
.disable_cpu = rtw89_mac_disable_cpu_be,
.fwdl_enable_wcpu = rtw89_mac_fwdl_enable_wcpu_be,
......
......@@ -5020,6 +5020,11 @@
#define B_BE_WDE_START_BOUND_MASK GENMASK(14, 8)
#define B_BE_WDE_PAGE_SEL_MASK GENMASK(1, 0)
#define R_BE_WDE_BUFMGN_CTL 0x8C10
#define B_BE_WDE_AVAL_UPD_REQ BIT(29)
#define B_BE_WDE_AVAL_UPD_QTAID_MASK GENMASK(27, 24)
#define B_BE_WDE_BUFMGN_FRZTMR_MODE BIT(0)
#define R_BE_WDE_ERR_IMR 0x8C38
#define B_BE_WDE_DATCHN_CAMREQ_ERR_INT_EN BIT(29)
#define B_BE_WDE_DATCHN_ADRERR_ERR_INT_EN BIT(28)
......@@ -5136,6 +5141,11 @@
#define B_BE_PLE_START_BOUND_MASK GENMASK(14, 8)
#define B_BE_PLE_PAGE_SEL_MASK GENMASK(1, 0)
#define R_BE_PLE_BUFMGN_CTL 0x9010
#define B_BE_PLE_AVAL_UPD_REQ BIT(29)
#define B_BE_PLE_AVAL_UPD_QTAID_MASK GENMASK(27, 24)
#define B_BE_PLE_BUFMGN_FRZTMR_MODE BIT(0)
#define R_BE_PLE_ERR_IMR 0x9038
#define B_BE_PLE_DATCHN_CAMREQ_ERR_INT_EN BIT(29)
#define B_BE_PLE_DATCHN_ADRERR_ERR_INT_EN BIT(28)
......
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