Commit b7c47fd7 authored by Will Deacon's avatar Will Deacon

Merge branch 'for-next/kcsan' into for-next/core

* for-next/kcsan:
  arm64: kcsan: Support detecting more missing memory barriers
  asm-generic: Add memory barrier dma_mb()
parents 570365d3 4d09caec
...@@ -1894,6 +1894,7 @@ There are some more advanced barrier functions: ...@@ -1894,6 +1894,7 @@ There are some more advanced barrier functions:
(*) dma_wmb(); (*) dma_wmb();
(*) dma_rmb(); (*) dma_rmb();
(*) dma_mb();
These are for use with consistent memory to guarantee the ordering These are for use with consistent memory to guarantee the ordering
of writes or reads of shared memory accessible to both the CPU and a of writes or reads of shared memory accessible to both the CPU and a
...@@ -1925,11 +1926,11 @@ There are some more advanced barrier functions: ...@@ -1925,11 +1926,11 @@ There are some more advanced barrier functions:
The dma_rmb() allows us guarantee the device has released ownership The dma_rmb() allows us guarantee the device has released ownership
before we read the data from the descriptor, and the dma_wmb() allows before we read the data from the descriptor, and the dma_wmb() allows
us to guarantee the data is written to the descriptor before the device us to guarantee the data is written to the descriptor before the device
can see it now has ownership. Note that, when using writel(), a prior can see it now has ownership. The dma_mb() implies both a dma_rmb() and
wmb() is not needed to guarantee that the cache coherent memory writes a dma_wmb(). Note that, when using writel(), a prior wmb() is not needed
have completed before writing to the MMIO region. The cheaper to guarantee that the cache coherent memory writes have completed before
writel_relaxed() does not provide this guarantee and must not be used writing to the MMIO region. The cheaper writel_relaxed() does not provide
here. this guarantee and must not be used here.
See the subsection "Kernel I/O barrier effects" for more information on See the subsection "Kernel I/O barrier effects" for more information on
relaxed I/O accessors and the Documentation/core-api/dma-api.rst file for relaxed I/O accessors and the Documentation/core-api/dma-api.rst file for
......
...@@ -50,13 +50,13 @@ ...@@ -50,13 +50,13 @@
#define pmr_sync() do {} while (0) #define pmr_sync() do {} while (0)
#endif #endif
#define mb() dsb(sy) #define __mb() dsb(sy)
#define rmb() dsb(ld) #define __rmb() dsb(ld)
#define wmb() dsb(st) #define __wmb() dsb(st)
#define dma_mb() dmb(osh) #define __dma_mb() dmb(osh)
#define dma_rmb() dmb(oshld) #define __dma_rmb() dmb(oshld)
#define dma_wmb() dmb(oshst) #define __dma_wmb() dmb(oshst)
#define io_stop_wc() dgh() #define io_stop_wc() dgh()
......
...@@ -38,6 +38,10 @@ ...@@ -38,6 +38,10 @@
#define wmb() do { kcsan_wmb(); __wmb(); } while (0) #define wmb() do { kcsan_wmb(); __wmb(); } while (0)
#endif #endif
#ifdef __dma_mb
#define dma_mb() do { kcsan_mb(); __dma_mb(); } while (0)
#endif
#ifdef __dma_rmb #ifdef __dma_rmb
#define dma_rmb() do { kcsan_rmb(); __dma_rmb(); } while (0) #define dma_rmb() do { kcsan_rmb(); __dma_rmb(); } while (0)
#endif #endif
...@@ -65,6 +69,10 @@ ...@@ -65,6 +69,10 @@
#define wmb() mb() #define wmb() mb()
#endif #endif
#ifndef dma_mb
#define dma_mb() mb()
#endif
#ifndef dma_rmb #ifndef dma_rmb
#define dma_rmb() rmb() #define dma_rmb() rmb()
#endif #endif
......
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