Commit b8a56e17 authored by Yoshihiro Shimoda's avatar Yoshihiro Shimoda Committed by Felipe Balbi

usb: gadget: r8a66597-udc: add support for SUDMAC

SH7757 has a USB function with internal DMA controller (SUDMAC).
This patch supports the SUDMAC. The SUDMAC is incompatible with
general-purpose DMAC. So, it doesn't use dmaengine.
Signed-off-by: default avatarYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: default avatarFelipe Balbi <balbi@ti.com>
parent 12158f42
This diff is collapsed.
...@@ -43,6 +43,7 @@ ...@@ -43,6 +43,7 @@
((pipenum >= R8A66597_BASE_PIPENUM_ISOC) && \ ((pipenum >= R8A66597_BASE_PIPENUM_ISOC) && \
(pipenum < (R8A66597_BASE_PIPENUM_ISOC + R8A66597_MAX_NUM_ISOC))) (pipenum < (R8A66597_BASE_PIPENUM_ISOC + R8A66597_MAX_NUM_ISOC)))
#define r8a66597_is_sudmac(r8a66597) (r8a66597->pdata->sudmac)
struct r8a66597_pipe_info { struct r8a66597_pipe_info {
u16 pipe; u16 pipe;
u16 epnum; u16 epnum;
...@@ -60,6 +61,7 @@ struct r8a66597_request { ...@@ -60,6 +61,7 @@ struct r8a66597_request {
struct r8a66597_ep { struct r8a66597_ep {
struct usb_ep ep; struct usb_ep ep;
struct r8a66597 *r8a66597; struct r8a66597 *r8a66597;
struct r8a66597_dma *dma;
struct list_head queue; struct list_head queue;
unsigned busy:1; unsigned busy:1;
...@@ -75,13 +77,20 @@ struct r8a66597_ep { ...@@ -75,13 +77,20 @@ struct r8a66597_ep {
unsigned char fifoaddr; unsigned char fifoaddr;
unsigned char fifosel; unsigned char fifosel;
unsigned char fifoctr; unsigned char fifoctr;
unsigned char fifotrn;
unsigned char pipectr; unsigned char pipectr;
unsigned char pipetre;
unsigned char pipetrn;
};
struct r8a66597_dma {
unsigned used:1;
unsigned dir:1; /* 1 = IN(write), 0 = OUT(read) */
}; };
struct r8a66597 { struct r8a66597 {
spinlock_t lock; spinlock_t lock;
void __iomem *reg; void __iomem *reg;
void __iomem *sudmac_reg;
#ifdef CONFIG_HAVE_CLK #ifdef CONFIG_HAVE_CLK
struct clk *clk; struct clk *clk;
...@@ -94,6 +103,7 @@ struct r8a66597 { ...@@ -94,6 +103,7 @@ struct r8a66597 {
struct r8a66597_ep ep[R8A66597_MAX_NUM_PIPE]; struct r8a66597_ep ep[R8A66597_MAX_NUM_PIPE];
struct r8a66597_ep *pipenum2ep[R8A66597_MAX_NUM_PIPE]; struct r8a66597_ep *pipenum2ep[R8A66597_MAX_NUM_PIPE];
struct r8a66597_ep *epaddr2ep[16]; struct r8a66597_ep *epaddr2ep[16];
struct r8a66597_dma dma;
struct timer_list timer; struct timer_list timer;
struct usb_request *ep0_req; /* for internal request */ struct usb_request *ep0_req; /* for internal request */
...@@ -251,7 +261,21 @@ static inline u16 get_xtal_from_pdata(struct r8a66597_platdata *pdata) ...@@ -251,7 +261,21 @@ static inline u16 get_xtal_from_pdata(struct r8a66597_platdata *pdata)
return clock; return clock;
} }
static inline u32 r8a66597_sudmac_read(struct r8a66597 *r8a66597,
unsigned long offset)
{
return ioread32(r8a66597->sudmac_reg + offset);
}
static inline void r8a66597_sudmac_write(struct r8a66597 *r8a66597, u32 val,
unsigned long offset)
{
iowrite32(val, r8a66597->sudmac_reg + offset);
}
#define get_pipectr_addr(pipenum) (PIPE1CTR + (pipenum - 1) * 2) #define get_pipectr_addr(pipenum) (PIPE1CTR + (pipenum - 1) * 2)
#define get_pipetre_addr(pipenum) (PIPE1TRE + (pipenum - 1) * 4)
#define get_pipetrn_addr(pipenum) (PIPE1TRN + (pipenum - 1) * 4)
#define enable_irq_ready(r8a66597, pipenum) \ #define enable_irq_ready(r8a66597, pipenum) \
enable_pipe_irq(r8a66597, pipenum, BRDYENB) enable_pipe_irq(r8a66597, pipenum, BRDYENB)
......
...@@ -48,6 +48,9 @@ struct r8a66597_platdata { ...@@ -48,6 +48,9 @@ struct r8a66597_platdata {
/* (external controller only) set one = WR0_N shorted to WR1_N */ /* (external controller only) set one = WR0_N shorted to WR1_N */
unsigned wr0_shorted_to_wr1:1; unsigned wr0_shorted_to_wr1:1;
/* set one = using SUDMAC */
unsigned sudmac:1;
}; };
/* Register definitions */ /* Register definitions */
...@@ -417,5 +420,62 @@ struct r8a66597_platdata { ...@@ -417,5 +420,62 @@ struct r8a66597_platdata {
#define USBSPD 0x00C0 #define USBSPD 0x00C0
#define RTPORT 0x0001 #define RTPORT 0x0001
/* SUDMAC registers */
#define CH0CFG 0x00
#define CH1CFG 0x04
#define CH0BA 0x10
#define CH1BA 0x14
#define CH0BBC 0x18
#define CH1BBC 0x1C
#define CH0CA 0x20
#define CH1CA 0x24
#define CH0CBC 0x28
#define CH1CBC 0x2C
#define CH0DEN 0x30
#define CH1DEN 0x34
#define DSTSCLR 0x38
#define DBUFCTRL 0x3C
#define DINTCTRL 0x40
#define DINTSTS 0x44
#define DINTSTSCLR 0x48
#define CH0SHCTRL 0x50
#define CH1SHCTRL 0x54
/* SUDMAC Configuration Registers */
#define SENDBUFM 0x1000 /* b12: Transmit Buffer Mode */
#define RCVENDM 0x0100 /* b8: Receive Data Transfer End Mode */
#define LBA_WAIT 0x0030 /* b5-4: Local Bus Access Wait */
/* DMA Enable Registers */
#define DEN 0x0001 /* b1: DMA Transfer Enable */
/* DMA Status Clear Register */
#define CH1STCLR 0x0002 /* b2: Ch1 DMA Status Clear */
#define CH0STCLR 0x0001 /* b1: Ch0 DMA Status Clear */
/* DMA Buffer Control Register */
#define CH1BUFW 0x0200 /* b9: Ch1 DMA Buffer Data Transfer Enable */
#define CH0BUFW 0x0100 /* b8: Ch0 DMA Buffer Data Transfer Enable */
#define CH1BUFS 0x0002 /* b2: Ch1 DMA Buffer Data Status */
#define CH0BUFS 0x0001 /* b1: Ch0 DMA Buffer Data Status */
/* DMA Interrupt Control Register */
#define CH1ERRE 0x0200 /* b9: Ch1 SHwy Res Err Detect Int Enable */
#define CH0ERRE 0x0100 /* b8: Ch0 SHwy Res Err Detect Int Enable */
#define CH1ENDE 0x0002 /* b2: Ch1 DMA Transfer End Int Enable */
#define CH0ENDE 0x0001 /* b1: Ch0 DMA Transfer End Int Enable */
/* DMA Interrupt Status Register */
#define CH1ERRS 0x0200 /* b9: Ch1 SHwy Res Err Detect Int Status */
#define CH0ERRS 0x0100 /* b8: Ch0 SHwy Res Err Detect Int Status */
#define CH1ENDS 0x0002 /* b2: Ch1 DMA Transfer End Int Status */
#define CH0ENDS 0x0001 /* b1: Ch0 DMA Transfer End Int Status */
/* DMA Interrupt Status Clear Register */
#define CH1ERRC 0x0200 /* b9: Ch1 SHwy Res Err Detect Int Stat Clear */
#define CH0ERRC 0x0100 /* b8: Ch0 SHwy Res Err Detect Int Stat Clear */
#define CH1ENDC 0x0002 /* b2: Ch1 DMA Transfer End Int Stat Clear */
#define CH0ENDC 0x0001 /* b1: Ch0 DMA Transfer End Int Stat Clear */
#endif /* __LINUX_USB_R8A66597_H */ #endif /* __LINUX_USB_R8A66597_H */
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