Commit b907194a authored by Anshumali Gaur's avatar Anshumali Gaur Committed by David S. Miller

octeontx2-af: Add debugfs support to dump NIX TM topology

This patch adds support to dump NIX transmit queue topology.
There are multiple levels of scheduling/shaping supported by
NIX and a packet traverses through multiple levels before sending
the packet out. At each level, there are set of scheduling/shaping
rules applied to a packet flow.

Each packet traverses through multiple levels
SQ->SMQ->TL4->TL3->TL2->TL1 and these levels are mapped in a parent-child
relationship.

This patch dumps the debug information related to all TM Levels in
the following way.

Example:
$ echo <nixlf> > /sys/kernel/debug/octeontx2/nix/tm_tree
$ cat /sys/kernel/debug/octeontx2/nix/tm_tree

A more desriptive set of registers at each level can be dumped
in the following way.

Example:
$ echo <nixlf> > /sys/kernel/debug/octeontx2/nix/tm_topo
$ cat /sys/kernel/debug/octeontx2/nix/tm_topo
Signed-off-by: default avatarAnshumali Gaur <agaur@marvell.com>
Reviewed-by: default avatarWojciech Drewek <wojciech.drewek@intel.com>
Reviewed-by: default avatarSimon Horman <horms@kernel.org>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent fd70f044
...@@ -76,6 +76,7 @@ struct rvu_debugfs { ...@@ -76,6 +76,7 @@ struct rvu_debugfs {
struct dump_ctx nix_cq_ctx; struct dump_ctx nix_cq_ctx;
struct dump_ctx nix_rq_ctx; struct dump_ctx nix_rq_ctx;
struct dump_ctx nix_sq_ctx; struct dump_ctx nix_sq_ctx;
struct dump_ctx nix_tm_ctx;
struct cpt_ctx cpt_ctx[MAX_CPT_BLKS]; struct cpt_ctx cpt_ctx[MAX_CPT_BLKS];
int npa_qsize_id; int npa_qsize_id;
int nix_qsize_id; int nix_qsize_id;
......
...@@ -429,6 +429,8 @@ ...@@ -429,6 +429,8 @@
#define NIX_AF_RX_ACTIVE_CYCLES_PCX(a) (0x4800 | (a) << 16) #define NIX_AF_RX_ACTIVE_CYCLES_PCX(a) (0x4800 | (a) << 16)
#define NIX_AF_LINKX_CFG(a) (0x4010 | (a) << 17) #define NIX_AF_LINKX_CFG(a) (0x4010 | (a) << 17)
#define NIX_AF_MDQX_IN_MD_COUNT(a) (0x14e0 | (a) << 16) #define NIX_AF_MDQX_IN_MD_COUNT(a) (0x14e0 | (a) << 16)
#define NIX_AF_SMQX_STATUS(a) (0x730 | (a) << 16)
#define NIX_AF_MDQX_OUT_MD_COUNT(a) (0xdb0 | (a) << 16)
#define NIX_PRIV_AF_INT_CFG (0x8000000) #define NIX_PRIV_AF_INT_CFG (0x8000000)
#define NIX_PRIV_LFX_CFG (0x8000010) #define NIX_PRIV_LFX_CFG (0x8000010)
...@@ -442,6 +444,11 @@ ...@@ -442,6 +444,11 @@
#define NIX_CONST_MAX_BPIDS GENMASK_ULL(23, 12) #define NIX_CONST_MAX_BPIDS GENMASK_ULL(23, 12)
#define NIX_CONST_SDP_CHANS GENMASK_ULL(11, 0) #define NIX_CONST_SDP_CHANS GENMASK_ULL(11, 0)
#define NIX_AF_MDQ_PARENT_MASK GENMASK_ULL(24, 16)
#define NIX_AF_TL4_PARENT_MASK GENMASK_ULL(23, 16)
#define NIX_AF_TL3_PARENT_MASK GENMASK_ULL(23, 16)
#define NIX_AF_TL2_PARENT_MASK GENMASK_ULL(20, 16)
/* SSO */ /* SSO */
#define SSO_AF_CONST (0x1000) #define SSO_AF_CONST (0x1000)
#define SSO_AF_CONST1 (0x1008) #define SSO_AF_CONST1 (0x1008)
......
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