Commit b910a020 authored by Robert Foss's avatar Robert Foss Committed by Rob Clark

drm/msm/dpu: Fix sm8250_mdp register length

The downstream dts lists this value as 0x494, and not
0x45c.

Fixes: af776a3e ("drm/msm/dpu: add SM8250 to hw catalog")
Signed-off-by: default avatarRobert Foss <robert.foss@linaro.org>
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Link: https://lore.kernel.org/r/20210628085033.9905-1-robert.foss@linaro.orgSigned-off-by: default avatarRob Clark <robdclark@chromium.org>
parent ff117646
...@@ -296,7 +296,7 @@ static const struct dpu_mdp_cfg sc7180_mdp[] = { ...@@ -296,7 +296,7 @@ static const struct dpu_mdp_cfg sc7180_mdp[] = {
static const struct dpu_mdp_cfg sm8250_mdp[] = { static const struct dpu_mdp_cfg sm8250_mdp[] = {
{ {
.name = "top_0", .id = MDP_TOP, .name = "top_0", .id = MDP_TOP,
.base = 0x0, .len = 0x45C, .base = 0x0, .len = 0x494,
.features = 0, .features = 0,
.highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */ .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */
.clk_ctrls[DPU_CLK_CTRL_VIG0] = { .clk_ctrls[DPU_CLK_CTRL_VIG0] = {
......
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