Commit b9610edc authored by Alex Deucher's avatar Alex Deucher

drm/amdgpu/pm/smu7: drop message about VI performance levels

Earlier chips only had two performance levels, but newer
ones potentially had more.  The message is harmless.  Drop the
message to avoid spamming the log.

Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1874Reviewed-by: default avatarEvan Quan <evan.quan@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent f2bde834
......@@ -3295,10 +3295,6 @@ static int smu7_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
request_ps->classification.ui_label);
data->mclk_ignore_signal = false;
PP_ASSERT_WITH_CODE(smu7_ps->performance_level_count == 2,
"VI should always have 2 performance levels",
);
max_limits = adev->pm.ac_power ?
&(hwmgr->dyn_state.max_clock_voltage_on_ac) :
&(hwmgr->dyn_state.max_clock_voltage_on_dc);
......
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