Commit b990f9b3 authored by Linus Torvalds's avatar Linus Torvalds

Merge tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC fixes from Olof Johansson:
 "Nothing controversial, just another batch of fixes:

   - Samsung/exynos fixes for more merge window fallout: build errors
     and warnings mostly, but also some clock/device setup issues on
     exynos4/5
   - PXA bug and warning fixes related to gpio and pinmux
   - IRQ domain conversion bugfixes for U300 and MSM
   - A regulator setup fix for U300"

* tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
  ARM: PXA2xx: MFP: fix potential direction bug
  ARM: PXA2xx: MFP: fix bug with MFP_LPM_KEEP_OUTPUT
  arm/sa1100: fix sa1100-rtc memory resource
  ARM: pxa: fix gpio wakeup setting
  ARM: SAMSUNG: add missing MMC_CAP2_BROKEN_VOLTAGE capability
  ARM: EXYNOS: Fix compilation error when CONFIG_OF is not defined
  ARM: EXYNOS: Fix resource on dev-dwmci.c
  ARM: S3C24XX: Fix build warning for S3C2410_PM
  ARM: mini2440_defconfig: Fix build error
  ARM: msm: Fix gic irqdomain support
  ARM: EXYNOS: Fix incorrect initialization of GIC
  ARM: EXYNOS: use 'exynos4-sdhci' as device name for sdhci controllers
  ARM: u300: bump all IRQ numbers by one
  ARM: ux300: Fix unimplementable regulation constraints
parents cd88e3a6 6e76538b
...@@ -10,7 +10,7 @@ / { ...@@ -10,7 +10,7 @@ / {
intc: interrupt-controller@02080000 { intc: interrupt-controller@02080000 {
compatible = "qcom,msm-8660-qgic"; compatible = "qcom,msm-8660-qgic";
interrupt-controller; interrupt-controller;
#interrupt-cells = <1>; #interrupt-cells = <3>;
reg = < 0x02080000 0x1000 >, reg = < 0x02080000 0x1000 >,
< 0x02081000 0x1000 >; < 0x02081000 0x1000 >;
}; };
...@@ -19,6 +19,6 @@ serial@19c400000 { ...@@ -19,6 +19,6 @@ serial@19c400000 {
compatible = "qcom,msm-hsuart", "qcom,msm-uart"; compatible = "qcom,msm-hsuart", "qcom,msm-uart";
reg = <0x19c40000 0x1000>, reg = <0x19c40000 0x1000>,
<0x19c00000 0x1000>; <0x19c00000 0x1000>;
interrupts = <195>; interrupts = <0 195 0x0>;
}; };
}; };
...@@ -14,6 +14,8 @@ CONFIG_MODULE_FORCE_UNLOAD=y ...@@ -14,6 +14,8 @@ CONFIG_MODULE_FORCE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set # CONFIG_BLK_DEV_BSG is not set
CONFIG_BLK_DEV_INTEGRITY=y CONFIG_BLK_DEV_INTEGRITY=y
CONFIG_ARCH_S3C24XX=y CONFIG_ARCH_S3C24XX=y
# CONFIG_CPU_S3C2410 is not set
CONFIG_CPU_S3C2440=y
CONFIG_S3C_ADC=y CONFIG_S3C_ADC=y
CONFIG_S3C24XX_PWM=y CONFIG_S3C24XX_PWM=y
CONFIG_MACH_MINI2440=y CONFIG_MACH_MINI2440=y
......
...@@ -497,25 +497,25 @@ static struct clk exynos4_init_clocks_off[] = { ...@@ -497,25 +497,25 @@ static struct clk exynos4_init_clocks_off[] = {
.ctrlbit = (1 << 3), .ctrlbit = (1 << 3),
}, { }, {
.name = "hsmmc", .name = "hsmmc",
.devname = "s3c-sdhci.0", .devname = "exynos4-sdhci.0",
.parent = &exynos4_clk_aclk_133.clk, .parent = &exynos4_clk_aclk_133.clk,
.enable = exynos4_clk_ip_fsys_ctrl, .enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 5), .ctrlbit = (1 << 5),
}, { }, {
.name = "hsmmc", .name = "hsmmc",
.devname = "s3c-sdhci.1", .devname = "exynos4-sdhci.1",
.parent = &exynos4_clk_aclk_133.clk, .parent = &exynos4_clk_aclk_133.clk,
.enable = exynos4_clk_ip_fsys_ctrl, .enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 6), .ctrlbit = (1 << 6),
}, { }, {
.name = "hsmmc", .name = "hsmmc",
.devname = "s3c-sdhci.2", .devname = "exynos4-sdhci.2",
.parent = &exynos4_clk_aclk_133.clk, .parent = &exynos4_clk_aclk_133.clk,
.enable = exynos4_clk_ip_fsys_ctrl, .enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 7), .ctrlbit = (1 << 7),
}, { }, {
.name = "hsmmc", .name = "hsmmc",
.devname = "s3c-sdhci.3", .devname = "exynos4-sdhci.3",
.parent = &exynos4_clk_aclk_133.clk, .parent = &exynos4_clk_aclk_133.clk,
.enable = exynos4_clk_ip_fsys_ctrl, .enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 8), .ctrlbit = (1 << 8),
...@@ -1202,7 +1202,7 @@ static struct clksrc_clk exynos4_clk_sclk_uart3 = { ...@@ -1202,7 +1202,7 @@ static struct clksrc_clk exynos4_clk_sclk_uart3 = {
static struct clksrc_clk exynos4_clk_sclk_mmc0 = { static struct clksrc_clk exynos4_clk_sclk_mmc0 = {
.clk = { .clk = {
.name = "sclk_mmc", .name = "sclk_mmc",
.devname = "s3c-sdhci.0", .devname = "exynos4-sdhci.0",
.parent = &exynos4_clk_dout_mmc0.clk, .parent = &exynos4_clk_dout_mmc0.clk,
.enable = exynos4_clksrc_mask_fsys_ctrl, .enable = exynos4_clksrc_mask_fsys_ctrl,
.ctrlbit = (1 << 0), .ctrlbit = (1 << 0),
...@@ -1213,7 +1213,7 @@ static struct clksrc_clk exynos4_clk_sclk_mmc0 = { ...@@ -1213,7 +1213,7 @@ static struct clksrc_clk exynos4_clk_sclk_mmc0 = {
static struct clksrc_clk exynos4_clk_sclk_mmc1 = { static struct clksrc_clk exynos4_clk_sclk_mmc1 = {
.clk = { .clk = {
.name = "sclk_mmc", .name = "sclk_mmc",
.devname = "s3c-sdhci.1", .devname = "exynos4-sdhci.1",
.parent = &exynos4_clk_dout_mmc1.clk, .parent = &exynos4_clk_dout_mmc1.clk,
.enable = exynos4_clksrc_mask_fsys_ctrl, .enable = exynos4_clksrc_mask_fsys_ctrl,
.ctrlbit = (1 << 4), .ctrlbit = (1 << 4),
...@@ -1224,7 +1224,7 @@ static struct clksrc_clk exynos4_clk_sclk_mmc1 = { ...@@ -1224,7 +1224,7 @@ static struct clksrc_clk exynos4_clk_sclk_mmc1 = {
static struct clksrc_clk exynos4_clk_sclk_mmc2 = { static struct clksrc_clk exynos4_clk_sclk_mmc2 = {
.clk = { .clk = {
.name = "sclk_mmc", .name = "sclk_mmc",
.devname = "s3c-sdhci.2", .devname = "exynos4-sdhci.2",
.parent = &exynos4_clk_dout_mmc2.clk, .parent = &exynos4_clk_dout_mmc2.clk,
.enable = exynos4_clksrc_mask_fsys_ctrl, .enable = exynos4_clksrc_mask_fsys_ctrl,
.ctrlbit = (1 << 8), .ctrlbit = (1 << 8),
...@@ -1235,7 +1235,7 @@ static struct clksrc_clk exynos4_clk_sclk_mmc2 = { ...@@ -1235,7 +1235,7 @@ static struct clksrc_clk exynos4_clk_sclk_mmc2 = {
static struct clksrc_clk exynos4_clk_sclk_mmc3 = { static struct clksrc_clk exynos4_clk_sclk_mmc3 = {
.clk = { .clk = {
.name = "sclk_mmc", .name = "sclk_mmc",
.devname = "s3c-sdhci.3", .devname = "exynos4-sdhci.3",
.parent = &exynos4_clk_dout_mmc3.clk, .parent = &exynos4_clk_dout_mmc3.clk,
.enable = exynos4_clksrc_mask_fsys_ctrl, .enable = exynos4_clksrc_mask_fsys_ctrl,
.ctrlbit = (1 << 12), .ctrlbit = (1 << 12),
...@@ -1340,10 +1340,10 @@ static struct clk_lookup exynos4_clk_lookup[] = { ...@@ -1340,10 +1340,10 @@ static struct clk_lookup exynos4_clk_lookup[] = {
CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos4_clk_sclk_uart1.clk), CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos4_clk_sclk_uart1.clk),
CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos4_clk_sclk_uart2.clk), CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos4_clk_sclk_uart2.clk),
CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos4_clk_sclk_uart3.clk), CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos4_clk_sclk_uart3.clk),
CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &exynos4_clk_sclk_mmc0.clk), CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &exynos4_clk_sclk_mmc0.clk),
CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &exynos4_clk_sclk_mmc1.clk), CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos4_clk_sclk_mmc1.clk),
CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &exynos4_clk_sclk_mmc2.clk), CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos4_clk_sclk_mmc2.clk),
CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &exynos4_clk_sclk_mmc3.clk), CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos4_clk_sclk_mmc3.clk),
CLKDEV_INIT("exynos4-fb.0", "lcd", &exynos4_clk_fimd0), CLKDEV_INIT("exynos4-fb.0", "lcd", &exynos4_clk_fimd0),
CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos4_clk_pdma0), CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos4_clk_pdma0),
CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos4_clk_pdma1), CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos4_clk_pdma1),
......
...@@ -455,25 +455,25 @@ static struct clk exynos5_init_clocks_off[] = { ...@@ -455,25 +455,25 @@ static struct clk exynos5_init_clocks_off[] = {
.ctrlbit = (1 << 20), .ctrlbit = (1 << 20),
}, { }, {
.name = "hsmmc", .name = "hsmmc",
.devname = "s3c-sdhci.0", .devname = "exynos4-sdhci.0",
.parent = &exynos5_clk_aclk_200.clk, .parent = &exynos5_clk_aclk_200.clk,
.enable = exynos5_clk_ip_fsys_ctrl, .enable = exynos5_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 12), .ctrlbit = (1 << 12),
}, { }, {
.name = "hsmmc", .name = "hsmmc",
.devname = "s3c-sdhci.1", .devname = "exynos4-sdhci.1",
.parent = &exynos5_clk_aclk_200.clk, .parent = &exynos5_clk_aclk_200.clk,
.enable = exynos5_clk_ip_fsys_ctrl, .enable = exynos5_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 13), .ctrlbit = (1 << 13),
}, { }, {
.name = "hsmmc", .name = "hsmmc",
.devname = "s3c-sdhci.2", .devname = "exynos4-sdhci.2",
.parent = &exynos5_clk_aclk_200.clk, .parent = &exynos5_clk_aclk_200.clk,
.enable = exynos5_clk_ip_fsys_ctrl, .enable = exynos5_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 14), .ctrlbit = (1 << 14),
}, { }, {
.name = "hsmmc", .name = "hsmmc",
.devname = "s3c-sdhci.3", .devname = "exynos4-sdhci.3",
.parent = &exynos5_clk_aclk_200.clk, .parent = &exynos5_clk_aclk_200.clk,
.enable = exynos5_clk_ip_fsys_ctrl, .enable = exynos5_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 15), .ctrlbit = (1 << 15),
...@@ -813,7 +813,7 @@ static struct clksrc_clk exynos5_clk_sclk_uart3 = { ...@@ -813,7 +813,7 @@ static struct clksrc_clk exynos5_clk_sclk_uart3 = {
static struct clksrc_clk exynos5_clk_sclk_mmc0 = { static struct clksrc_clk exynos5_clk_sclk_mmc0 = {
.clk = { .clk = {
.name = "sclk_mmc", .name = "sclk_mmc",
.devname = "s3c-sdhci.0", .devname = "exynos4-sdhci.0",
.parent = &exynos5_clk_dout_mmc0.clk, .parent = &exynos5_clk_dout_mmc0.clk,
.enable = exynos5_clksrc_mask_fsys_ctrl, .enable = exynos5_clksrc_mask_fsys_ctrl,
.ctrlbit = (1 << 0), .ctrlbit = (1 << 0),
...@@ -824,7 +824,7 @@ static struct clksrc_clk exynos5_clk_sclk_mmc0 = { ...@@ -824,7 +824,7 @@ static struct clksrc_clk exynos5_clk_sclk_mmc0 = {
static struct clksrc_clk exynos5_clk_sclk_mmc1 = { static struct clksrc_clk exynos5_clk_sclk_mmc1 = {
.clk = { .clk = {
.name = "sclk_mmc", .name = "sclk_mmc",
.devname = "s3c-sdhci.1", .devname = "exynos4-sdhci.1",
.parent = &exynos5_clk_dout_mmc1.clk, .parent = &exynos5_clk_dout_mmc1.clk,
.enable = exynos5_clksrc_mask_fsys_ctrl, .enable = exynos5_clksrc_mask_fsys_ctrl,
.ctrlbit = (1 << 4), .ctrlbit = (1 << 4),
...@@ -835,7 +835,7 @@ static struct clksrc_clk exynos5_clk_sclk_mmc1 = { ...@@ -835,7 +835,7 @@ static struct clksrc_clk exynos5_clk_sclk_mmc1 = {
static struct clksrc_clk exynos5_clk_sclk_mmc2 = { static struct clksrc_clk exynos5_clk_sclk_mmc2 = {
.clk = { .clk = {
.name = "sclk_mmc", .name = "sclk_mmc",
.devname = "s3c-sdhci.2", .devname = "exynos4-sdhci.2",
.parent = &exynos5_clk_dout_mmc2.clk, .parent = &exynos5_clk_dout_mmc2.clk,
.enable = exynos5_clksrc_mask_fsys_ctrl, .enable = exynos5_clksrc_mask_fsys_ctrl,
.ctrlbit = (1 << 8), .ctrlbit = (1 << 8),
...@@ -846,7 +846,7 @@ static struct clksrc_clk exynos5_clk_sclk_mmc2 = { ...@@ -846,7 +846,7 @@ static struct clksrc_clk exynos5_clk_sclk_mmc2 = {
static struct clksrc_clk exynos5_clk_sclk_mmc3 = { static struct clksrc_clk exynos5_clk_sclk_mmc3 = {
.clk = { .clk = {
.name = "sclk_mmc", .name = "sclk_mmc",
.devname = "s3c-sdhci.3", .devname = "exynos4-sdhci.3",
.parent = &exynos5_clk_dout_mmc3.clk, .parent = &exynos5_clk_dout_mmc3.clk,
.enable = exynos5_clksrc_mask_fsys_ctrl, .enable = exynos5_clksrc_mask_fsys_ctrl,
.ctrlbit = (1 << 12), .ctrlbit = (1 << 12),
...@@ -990,10 +990,10 @@ static struct clk_lookup exynos5_clk_lookup[] = { ...@@ -990,10 +990,10 @@ static struct clk_lookup exynos5_clk_lookup[] = {
CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos5_clk_sclk_uart1.clk), CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos5_clk_sclk_uart1.clk),
CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos5_clk_sclk_uart2.clk), CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos5_clk_sclk_uart2.clk),
CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos5_clk_sclk_uart3.clk), CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos5_clk_sclk_uart3.clk),
CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &exynos5_clk_sclk_mmc0.clk), CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &exynos5_clk_sclk_mmc0.clk),
CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &exynos5_clk_sclk_mmc1.clk), CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos5_clk_sclk_mmc1.clk),
CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &exynos5_clk_sclk_mmc2.clk), CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos5_clk_sclk_mmc2.clk),
CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &exynos5_clk_sclk_mmc3.clk), CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos5_clk_sclk_mmc3.clk),
CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos5_clk_pdma0), CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos5_clk_pdma0),
CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos5_clk_pdma1), CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos5_clk_pdma1),
CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos5_clk_mdma1), CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos5_clk_mdma1),
......
...@@ -326,6 +326,11 @@ static void __init exynos4_map_io(void) ...@@ -326,6 +326,11 @@ static void __init exynos4_map_io(void)
s3c_fimc_setname(2, "exynos4-fimc"); s3c_fimc_setname(2, "exynos4-fimc");
s3c_fimc_setname(3, "exynos4-fimc"); s3c_fimc_setname(3, "exynos4-fimc");
s3c_sdhci_setname(0, "exynos4-sdhci");
s3c_sdhci_setname(1, "exynos4-sdhci");
s3c_sdhci_setname(2, "exynos4-sdhci");
s3c_sdhci_setname(3, "exynos4-sdhci");
/* The I2C bus controllers are directly compatible with s3c2440 */ /* The I2C bus controllers are directly compatible with s3c2440 */
s3c_i2c0_setname("s3c2440-i2c"); s3c_i2c0_setname("s3c2440-i2c");
s3c_i2c1_setname("s3c2440-i2c"); s3c_i2c1_setname("s3c2440-i2c");
...@@ -344,6 +349,11 @@ static void __init exynos5_map_io(void) ...@@ -344,6 +349,11 @@ static void __init exynos5_map_io(void)
s3c_device_i2c0.resource[1].start = EXYNOS5_IRQ_IIC; s3c_device_i2c0.resource[1].start = EXYNOS5_IRQ_IIC;
s3c_device_i2c0.resource[1].end = EXYNOS5_IRQ_IIC; s3c_device_i2c0.resource[1].end = EXYNOS5_IRQ_IIC;
s3c_sdhci_setname(0, "exynos4-sdhci");
s3c_sdhci_setname(1, "exynos4-sdhci");
s3c_sdhci_setname(2, "exynos4-sdhci");
s3c_sdhci_setname(3, "exynos4-sdhci");
/* The I2C bus controllers are directly compatible with s3c2440 */ /* The I2C bus controllers are directly compatible with s3c2440 */
s3c_i2c0_setname("s3c2440-i2c"); s3c_i2c0_setname("s3c2440-i2c");
s3c_i2c1_setname("s3c2440-i2c"); s3c_i2c1_setname("s3c2440-i2c");
...@@ -537,7 +547,9 @@ void __init exynos5_init_irq(void) ...@@ -537,7 +547,9 @@ void __init exynos5_init_irq(void)
{ {
int irq; int irq;
gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU); #ifdef CONFIG_OF
of_irq_init(exynos4_dt_irq_match);
#endif
for (irq = 0; irq < EXYNOS5_MAX_COMBINER_NR; irq++) { for (irq = 0; irq < EXYNOS5_MAX_COMBINER_NR; irq++) {
combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq), combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
......
...@@ -16,6 +16,7 @@ ...@@ -16,6 +16,7 @@
#include <linux/dma-mapping.h> #include <linux/dma-mapping.h>
#include <linux/platform_device.h> #include <linux/platform_device.h>
#include <linux/interrupt.h> #include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/mmc/dw_mmc.h> #include <linux/mmc/dw_mmc.h>
#include <plat/devs.h> #include <plat/devs.h>
...@@ -33,16 +34,8 @@ static int exynos4_dwmci_init(u32 slot_id, irq_handler_t handler, void *data) ...@@ -33,16 +34,8 @@ static int exynos4_dwmci_init(u32 slot_id, irq_handler_t handler, void *data)
} }
static struct resource exynos4_dwmci_resource[] = { static struct resource exynos4_dwmci_resource[] = {
[0] = { [0] = DEFINE_RES_MEM(EXYNOS4_PA_DWMCI, SZ_4K),
.start = EXYNOS4_PA_DWMCI, [1] = DEFINE_RES_IRQ(EXYNOS4_IRQ_DWMCI),
.end = EXYNOS4_PA_DWMCI + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_DWMCI,
.end = IRQ_DWMCI,
.flags = IORESOURCE_IRQ,
}
}; };
static struct dw_mci_board exynos4_dwci_pdata = { static struct dw_mci_board exynos4_dwci_pdata = {
......
...@@ -112,6 +112,7 @@ static struct s3c_sdhci_platdata nuri_hsmmc0_data __initdata = { ...@@ -112,6 +112,7 @@ static struct s3c_sdhci_platdata nuri_hsmmc0_data __initdata = {
.host_caps = (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA | .host_caps = (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA |
MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
MMC_CAP_ERASE), MMC_CAP_ERASE),
.host_caps2 = MMC_CAP2_BROKEN_VOLTAGE,
.cd_type = S3C_SDHCI_CD_PERMANENT, .cd_type = S3C_SDHCI_CD_PERMANENT,
.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
}; };
......
...@@ -747,6 +747,7 @@ static struct s3c_sdhci_platdata universal_hsmmc0_data __initdata = { ...@@ -747,6 +747,7 @@ static struct s3c_sdhci_platdata universal_hsmmc0_data __initdata = {
.max_width = 8, .max_width = 8,
.host_caps = (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA | .host_caps = (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA |
MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED), MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
.host_caps2 = MMC_CAP2_BROKEN_VOLTAGE,
.cd_type = S3C_SDHCI_CD_PERMANENT, .cd_type = S3C_SDHCI_CD_PERMANENT,
.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
}; };
......
...@@ -17,6 +17,7 @@ ...@@ -17,6 +17,7 @@
#include <linux/irqdomain.h> #include <linux/irqdomain.h>
#include <linux/of.h> #include <linux/of.h>
#include <linux/of_address.h> #include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h> #include <linux/of_platform.h>
#include <linux/memblock.h> #include <linux/memblock.h>
...@@ -49,10 +50,22 @@ static void __init msm8x60_map_io(void) ...@@ -49,10 +50,22 @@ static void __init msm8x60_map_io(void)
msm_map_msm8x60_io(); msm_map_msm8x60_io();
} }
#ifdef CONFIG_OF
static struct of_device_id msm_dt_gic_match[] __initdata = {
{ .compatible = "qcom,msm-8660-qgic", .data = gic_of_init },
{}
};
#endif
static void __init msm8x60_init_irq(void) static void __init msm8x60_init_irq(void)
{ {
gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE, if (!of_have_populated_dt())
(void *)MSM_QGIC_CPU_BASE); gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE,
(void *)MSM_QGIC_CPU_BASE);
#ifdef CONFIG_OF
else
of_irq_init(msm_dt_gic_match);
#endif
/* Edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */ /* Edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */
writel(0xFFFFD7FF, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4); writel(0xFFFFD7FF, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4);
...@@ -73,16 +86,8 @@ static struct of_dev_auxdata msm_auxdata_lookup[] __initdata = { ...@@ -73,16 +86,8 @@ static struct of_dev_auxdata msm_auxdata_lookup[] __initdata = {
{} {}
}; };
static struct of_device_id msm_dt_gic_match[] __initdata = {
{ .compatible = "qcom,msm-8660-qgic", },
{}
};
static void __init msm8x60_dt_init(void) static void __init msm8x60_dt_init(void)
{ {
irq_domain_generate_simple(msm_dt_gic_match, MSM8X60_QGIC_DIST_PHYS,
GIC_SPI_START);
if (of_machine_is_compatible("qcom,msm8660-surf")) { if (of_machine_is_compatible("qcom,msm8660-surf")) {
printk(KERN_INFO "Init surf UART registers\n"); printk(KERN_INFO "Init surf UART registers\n");
msm8x60_init_uart12dm(); msm8x60_init_uart12dm();
......
...@@ -17,6 +17,7 @@ ...@@ -17,6 +17,7 @@
* *
* bit 23 - Input/Output (PXA2xx specific) * bit 23 - Input/Output (PXA2xx specific)
* bit 24 - Wakeup Enable(PXA2xx specific) * bit 24 - Wakeup Enable(PXA2xx specific)
* bit 25 - Keep Output (PXA2xx specific)
*/ */
#define MFP_DIR_IN (0x0 << 23) #define MFP_DIR_IN (0x0 << 23)
...@@ -25,6 +26,12 @@ ...@@ -25,6 +26,12 @@
#define MFP_DIR(x) (((x) >> 23) & 0x1) #define MFP_DIR(x) (((x) >> 23) & 0x1)
#define MFP_LPM_CAN_WAKEUP (0x1 << 24) #define MFP_LPM_CAN_WAKEUP (0x1 << 24)
/*
* MFP_LPM_KEEP_OUTPUT must be specified for pins that need to
* retain their last output level (low or high).
* Note: MFP_LPM_KEEP_OUTPUT has no effect on pins configured for input.
*/
#define MFP_LPM_KEEP_OUTPUT (0x1 << 25) #define MFP_LPM_KEEP_OUTPUT (0x1 << 25)
#define WAKEUP_ON_EDGE_RISE (MFP_LPM_CAN_WAKEUP | MFP_LPM_EDGE_RISE) #define WAKEUP_ON_EDGE_RISE (MFP_LPM_CAN_WAKEUP | MFP_LPM_EDGE_RISE)
......
...@@ -33,6 +33,8 @@ ...@@ -33,6 +33,8 @@
#define BANK_OFF(n) (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2)) #define BANK_OFF(n) (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2))
#define GPLR(x) __REG2(0x40E00000, BANK_OFF((x) >> 5)) #define GPLR(x) __REG2(0x40E00000, BANK_OFF((x) >> 5))
#define GPDR(x) __REG2(0x40E00000, BANK_OFF((x) >> 5) + 0x0c) #define GPDR(x) __REG2(0x40E00000, BANK_OFF((x) >> 5) + 0x0c)
#define GPSR(x) __REG2(0x40E00000, BANK_OFF((x) >> 5) + 0x18)
#define GPCR(x) __REG2(0x40E00000, BANK_OFF((x) >> 5) + 0x24)
#define PWER_WE35 (1 << 24) #define PWER_WE35 (1 << 24)
...@@ -348,6 +350,7 @@ static inline void pxa27x_mfp_init(void) {} ...@@ -348,6 +350,7 @@ static inline void pxa27x_mfp_init(void) {}
#ifdef CONFIG_PM #ifdef CONFIG_PM
static unsigned long saved_gafr[2][4]; static unsigned long saved_gafr[2][4];
static unsigned long saved_gpdr[4]; static unsigned long saved_gpdr[4];
static unsigned long saved_gplr[4];
static unsigned long saved_pgsr[4]; static unsigned long saved_pgsr[4];
static int pxa2xx_mfp_suspend(void) static int pxa2xx_mfp_suspend(void)
...@@ -366,14 +369,26 @@ static int pxa2xx_mfp_suspend(void) ...@@ -366,14 +369,26 @@ static int pxa2xx_mfp_suspend(void)
} }
for (i = 0; i <= gpio_to_bank(pxa_last_gpio); i++) { for (i = 0; i <= gpio_to_bank(pxa_last_gpio); i++) {
saved_gafr[0][i] = GAFR_L(i); saved_gafr[0][i] = GAFR_L(i);
saved_gafr[1][i] = GAFR_U(i); saved_gafr[1][i] = GAFR_U(i);
saved_gpdr[i] = GPDR(i * 32); saved_gpdr[i] = GPDR(i * 32);
saved_gplr[i] = GPLR(i * 32);
saved_pgsr[i] = PGSR(i); saved_pgsr[i] = PGSR(i);
GPDR(i * 32) = gpdr_lpm[i]; GPSR(i * 32) = PGSR(i);
GPCR(i * 32) = ~PGSR(i);
}
/* set GPDR bits taking into account MFP_LPM_KEEP_OUTPUT */
for (i = 0; i < pxa_last_gpio; i++) {
if ((gpdr_lpm[gpio_to_bank(i)] & GPIO_bit(i)) ||
((gpio_desc[i].config & MFP_LPM_KEEP_OUTPUT) &&
(saved_gpdr[gpio_to_bank(i)] & GPIO_bit(i))))
GPDR(i) |= GPIO_bit(i);
else
GPDR(i) &= ~GPIO_bit(i);
} }
return 0; return 0;
} }
...@@ -384,6 +399,8 @@ static void pxa2xx_mfp_resume(void) ...@@ -384,6 +399,8 @@ static void pxa2xx_mfp_resume(void)
for (i = 0; i <= gpio_to_bank(pxa_last_gpio); i++) { for (i = 0; i <= gpio_to_bank(pxa_last_gpio); i++) {
GAFR_L(i) = saved_gafr[0][i]; GAFR_L(i) = saved_gafr[0][i];
GAFR_U(i) = saved_gafr[1][i]; GAFR_U(i) = saved_gafr[1][i];
GPSR(i * 32) = saved_gplr[i];
GPCR(i * 32) = ~saved_gplr[i];
GPDR(i * 32) = saved_gpdr[i]; GPDR(i * 32) = saved_gpdr[i];
PGSR(i) = saved_pgsr[i]; PGSR(i) = saved_pgsr[i];
} }
......
...@@ -421,8 +421,11 @@ void __init pxa27x_set_i2c_power_info(struct i2c_pxa_platform_data *info) ...@@ -421,8 +421,11 @@ void __init pxa27x_set_i2c_power_info(struct i2c_pxa_platform_data *info)
pxa_register_device(&pxa27x_device_i2c_power, info); pxa_register_device(&pxa27x_device_i2c_power, info);
} }
static struct pxa_gpio_platform_data pxa27x_gpio_info __initdata = {
.gpio_set_wake = gpio_set_wake,
};
static struct platform_device *devices[] __initdata = { static struct platform_device *devices[] __initdata = {
&pxa_device_gpio,
&pxa27x_device_udc, &pxa27x_device_udc,
&pxa_device_pmu, &pxa_device_pmu,
&pxa_device_i2s, &pxa_device_i2s,
...@@ -458,6 +461,7 @@ static int __init pxa27x_init(void) ...@@ -458,6 +461,7 @@ static int __init pxa27x_init(void)
register_syscore_ops(&pxa2xx_mfp_syscore_ops); register_syscore_ops(&pxa2xx_mfp_syscore_ops);
register_syscore_ops(&pxa2xx_clock_syscore_ops); register_syscore_ops(&pxa2xx_clock_syscore_ops);
pxa_register_device(&pxa_device_gpio, &pxa27x_gpio_info);
ret = platform_add_devices(devices, ARRAY_SIZE(devices)); ret = platform_add_devices(devices, ARRAY_SIZE(devices));
} }
......
...@@ -111,10 +111,6 @@ config S3C24XX_SETUP_TS ...@@ -111,10 +111,6 @@ config S3C24XX_SETUP_TS
help help
Compile in platform device definition for Samsung TouchScreen. Compile in platform device definition for Samsung TouchScreen.
# cpu-specific sections
if CPU_S3C2410
config S3C2410_DMA config S3C2410_DMA
bool bool
depends on S3C24XX_DMA && (CPU_S3C2410 || CPU_S3C2442) depends on S3C24XX_DMA && (CPU_S3C2410 || CPU_S3C2442)
...@@ -127,6 +123,10 @@ config S3C2410_PM ...@@ -127,6 +123,10 @@ config S3C2410_PM
help help
Power Management code common to S3C2410 and better Power Management code common to S3C2410 and better
# cpu-specific sections
if CPU_S3C2410
config S3C24XX_SIMTEC_NOR config S3C24XX_SIMTEC_NOR
bool bool
help help
......
...@@ -25,6 +25,7 @@ ...@@ -25,6 +25,7 @@
#include <linux/gpio_keys.h> #include <linux/gpio_keys.h>
#include <linux/input.h> #include <linux/input.h>
#include <linux/gpio.h> #include <linux/gpio.h>
#include <linux/mmc/host.h>
#include <linux/interrupt.h> #include <linux/interrupt.h>
#include <asm/hardware/vic.h> #include <asm/hardware/vic.h>
...@@ -765,6 +766,7 @@ static void __init goni_pmic_init(void) ...@@ -765,6 +766,7 @@ static void __init goni_pmic_init(void)
/* MoviNAND */ /* MoviNAND */
static struct s3c_sdhci_platdata goni_hsmmc0_data __initdata = { static struct s3c_sdhci_platdata goni_hsmmc0_data __initdata = {
.max_width = 4, .max_width = 4,
.host_caps2 = MMC_CAP2_BROKEN_VOLTAGE,
.cd_type = S3C_SDHCI_CD_PERMANENT, .cd_type = S3C_SDHCI_CD_PERMANENT,
}; };
......
...@@ -306,7 +306,7 @@ void sa11x0_register_irda(struct irda_platform_data *irda) ...@@ -306,7 +306,7 @@ void sa11x0_register_irda(struct irda_platform_data *irda)
} }
static struct resource sa1100_rtc_resources[] = { static struct resource sa1100_rtc_resources[] = {
DEFINE_RES_MEM(0x90010000, 0x9001003f), DEFINE_RES_MEM(0x90010000, 0x40),
DEFINE_RES_IRQ_NAMED(IRQ_RTC1Hz, "rtc 1Hz"), DEFINE_RES_IRQ_NAMED(IRQ_RTC1Hz, "rtc 1Hz"),
DEFINE_RES_IRQ_NAMED(IRQ_RTCAlrm, "rtc alarm"), DEFINE_RES_IRQ_NAMED(IRQ_RTCAlrm, "rtc alarm"),
}; };
......
...@@ -1667,8 +1667,10 @@ void __init u300_init_irq(void) ...@@ -1667,8 +1667,10 @@ void __init u300_init_irq(void)
for (i = 0; i < U300_VIC_IRQS_END; i++) for (i = 0; i < U300_VIC_IRQS_END; i++)
set_bit(i, (unsigned long *) &mask[0]); set_bit(i, (unsigned long *) &mask[0]);
vic_init((void __iomem *) U300_INTCON0_VBASE, 0, mask[0], mask[0]); vic_init((void __iomem *) U300_INTCON0_VBASE, IRQ_U300_INTCON0_START,
vic_init((void __iomem *) U300_INTCON1_VBASE, 32, mask[1], mask[1]); mask[0], mask[0]);
vic_init((void __iomem *) U300_INTCON1_VBASE, IRQ_U300_INTCON1_START,
mask[1], mask[1]);
} }
......
...@@ -146,9 +146,6 @@ static struct ab3100_platform_data ab3100_plf_data = { ...@@ -146,9 +146,6 @@ static struct ab3100_platform_data ab3100_plf_data = {
.min_uV = 1800000, .min_uV = 1800000,
.max_uV = 1800000, .max_uV = 1800000,
.valid_modes_mask = REGULATOR_MODE_NORMAL, .valid_modes_mask = REGULATOR_MODE_NORMAL,
.valid_ops_mask =
REGULATOR_CHANGE_VOLTAGE |
REGULATOR_CHANGE_STATUS,
.always_on = 1, .always_on = 1,
.boot_on = 1, .boot_on = 1,
}, },
...@@ -160,9 +157,6 @@ static struct ab3100_platform_data ab3100_plf_data = { ...@@ -160,9 +157,6 @@ static struct ab3100_platform_data ab3100_plf_data = {
.min_uV = 2500000, .min_uV = 2500000,
.max_uV = 2500000, .max_uV = 2500000,
.valid_modes_mask = REGULATOR_MODE_NORMAL, .valid_modes_mask = REGULATOR_MODE_NORMAL,
.valid_ops_mask =
REGULATOR_CHANGE_VOLTAGE |
REGULATOR_CHANGE_STATUS,
.always_on = 1, .always_on = 1,
.boot_on = 1, .boot_on = 1,
}, },
...@@ -230,8 +224,7 @@ static struct ab3100_platform_data ab3100_plf_data = { ...@@ -230,8 +224,7 @@ static struct ab3100_platform_data ab3100_plf_data = {
.max_uV = 1800000, .max_uV = 1800000,
.valid_modes_mask = REGULATOR_MODE_NORMAL, .valid_modes_mask = REGULATOR_MODE_NORMAL,
.valid_ops_mask = .valid_ops_mask =
REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_VOLTAGE,
REGULATOR_CHANGE_STATUS,
.always_on = 1, .always_on = 1,
.boot_on = 1, .boot_on = 1,
}, },
......
...@@ -12,101 +12,101 @@ ...@@ -12,101 +12,101 @@
#ifndef __MACH_IRQS_H #ifndef __MACH_IRQS_H
#define __MACH_IRQS_H #define __MACH_IRQS_H
#define IRQ_U300_INTCON0_START 0 #define IRQ_U300_INTCON0_START 1
#define IRQ_U300_INTCON1_START 32 #define IRQ_U300_INTCON1_START 33
/* These are on INTCON0 - 30 lines */ /* These are on INTCON0 - 30 lines */
#define IRQ_U300_IRQ0_EXT 0 #define IRQ_U300_IRQ0_EXT 1
#define IRQ_U300_IRQ1_EXT 1 #define IRQ_U300_IRQ1_EXT 2
#define IRQ_U300_DMA 2 #define IRQ_U300_DMA 3
#define IRQ_U300_VIDEO_ENC_0 3 #define IRQ_U300_VIDEO_ENC_0 4
#define IRQ_U300_VIDEO_ENC_1 4 #define IRQ_U300_VIDEO_ENC_1 5
#define IRQ_U300_AAIF_RX 5 #define IRQ_U300_AAIF_RX 6
#define IRQ_U300_AAIF_TX 6 #define IRQ_U300_AAIF_TX 7
#define IRQ_U300_AAIF_VGPIO 7 #define IRQ_U300_AAIF_VGPIO 8
#define IRQ_U300_AAIF_WAKEUP 8 #define IRQ_U300_AAIF_WAKEUP 9
#define IRQ_U300_PCM_I2S0_FRAME 9 #define IRQ_U300_PCM_I2S0_FRAME 10
#define IRQ_U300_PCM_I2S0_FIFO 10 #define IRQ_U300_PCM_I2S0_FIFO 11
#define IRQ_U300_PCM_I2S1_FRAME 11 #define IRQ_U300_PCM_I2S1_FRAME 12
#define IRQ_U300_PCM_I2S1_FIFO 12 #define IRQ_U300_PCM_I2S1_FIFO 13
#define IRQ_U300_XGAM_GAMCON 13 #define IRQ_U300_XGAM_GAMCON 14
#define IRQ_U300_XGAM_CDI 14 #define IRQ_U300_XGAM_CDI 15
#define IRQ_U300_XGAM_CDICON 15 #define IRQ_U300_XGAM_CDICON 16
#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330) #if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330)
/* MMIACC not used on the DB3210 or DB3350 chips */ /* MMIACC not used on the DB3210 or DB3350 chips */
#define IRQ_U300_XGAM_MMIACC 16 #define IRQ_U300_XGAM_MMIACC 17
#endif #endif
#define IRQ_U300_XGAM_PDI 17 #define IRQ_U300_XGAM_PDI 18
#define IRQ_U300_XGAM_PDICON 18 #define IRQ_U300_XGAM_PDICON 19
#define IRQ_U300_XGAM_GAMEACC 19 #define IRQ_U300_XGAM_GAMEACC 20
#define IRQ_U300_XGAM_MCIDCT 20 #define IRQ_U300_XGAM_MCIDCT 21
#define IRQ_U300_APEX 21 #define IRQ_U300_APEX 22
#define IRQ_U300_UART0 22 #define IRQ_U300_UART0 23
#define IRQ_U300_SPI 23 #define IRQ_U300_SPI 24
#define IRQ_U300_TIMER_APP_OS 24 #define IRQ_U300_TIMER_APP_OS 25
#define IRQ_U300_TIMER_APP_DD 25 #define IRQ_U300_TIMER_APP_DD 26
#define IRQ_U300_TIMER_APP_GP1 26 #define IRQ_U300_TIMER_APP_GP1 27
#define IRQ_U300_TIMER_APP_GP2 27 #define IRQ_U300_TIMER_APP_GP2 28
#define IRQ_U300_TIMER_OS 28 #define IRQ_U300_TIMER_OS 29
#define IRQ_U300_TIMER_MS 29 #define IRQ_U300_TIMER_MS 30
#define IRQ_U300_KEYPAD_KEYBF 30 #define IRQ_U300_KEYPAD_KEYBF 31
#define IRQ_U300_KEYPAD_KEYBR 31 #define IRQ_U300_KEYPAD_KEYBR 32
/* These are on INTCON1 - 32 lines */ /* These are on INTCON1 - 32 lines */
#define IRQ_U300_GPIO_PORT0 32 #define IRQ_U300_GPIO_PORT0 33
#define IRQ_U300_GPIO_PORT1 33 #define IRQ_U300_GPIO_PORT1 34
#define IRQ_U300_GPIO_PORT2 34 #define IRQ_U300_GPIO_PORT2 35
#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330) || \ #if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330) || \
defined(CONFIG_MACH_U300_BS335) defined(CONFIG_MACH_U300_BS335)
/* These are for DB3150, DB3200 and DB3350 */ /* These are for DB3150, DB3200 and DB3350 */
#define IRQ_U300_WDOG 35 #define IRQ_U300_WDOG 36
#define IRQ_U300_EVHIST 36 #define IRQ_U300_EVHIST 37
#define IRQ_U300_MSPRO 37 #define IRQ_U300_MSPRO 38
#define IRQ_U300_MMCSD_MCIINTR0 38 #define IRQ_U300_MMCSD_MCIINTR0 39
#define IRQ_U300_MMCSD_MCIINTR1 39 #define IRQ_U300_MMCSD_MCIINTR1 40
#define IRQ_U300_I2C0 40 #define IRQ_U300_I2C0 41
#define IRQ_U300_I2C1 41 #define IRQ_U300_I2C1 42
#define IRQ_U300_RTC 42 #define IRQ_U300_RTC 43
#define IRQ_U300_NFIF 43 #define IRQ_U300_NFIF 44
#define IRQ_U300_NFIF2 44 #define IRQ_U300_NFIF2 45
#endif #endif
/* DB3150 and DB3200 have only 45 IRQs */ /* DB3150 and DB3200 have only 45 IRQs */
#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330) #if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330)
#define U300_VIC_IRQS_END 45 #define U300_VIC_IRQS_END 46
#endif #endif
/* The DB3350-specific interrupt lines */ /* The DB3350-specific interrupt lines */
#ifdef CONFIG_MACH_U300_BS335 #ifdef CONFIG_MACH_U300_BS335
#define IRQ_U300_ISP_F0 45 #define IRQ_U300_ISP_F0 46
#define IRQ_U300_ISP_F1 46 #define IRQ_U300_ISP_F1 47
#define IRQ_U300_ISP_F2 47 #define IRQ_U300_ISP_F2 48
#define IRQ_U300_ISP_F3 48 #define IRQ_U300_ISP_F3 49
#define IRQ_U300_ISP_F4 49 #define IRQ_U300_ISP_F4 50
#define IRQ_U300_GPIO_PORT3 50 #define IRQ_U300_GPIO_PORT3 51
#define IRQ_U300_SYSCON_PLL_LOCK 51 #define IRQ_U300_SYSCON_PLL_LOCK 52
#define IRQ_U300_UART1 52 #define IRQ_U300_UART1 53
#define IRQ_U300_GPIO_PORT4 53 #define IRQ_U300_GPIO_PORT4 54
#define IRQ_U300_GPIO_PORT5 54 #define IRQ_U300_GPIO_PORT5 55
#define IRQ_U300_GPIO_PORT6 55 #define IRQ_U300_GPIO_PORT6 56
#define U300_VIC_IRQS_END 56 #define U300_VIC_IRQS_END 57
#endif #endif
/* The DB3210-specific interrupt lines */ /* The DB3210-specific interrupt lines */
#ifdef CONFIG_MACH_U300_BS365 #ifdef CONFIG_MACH_U300_BS365
#define IRQ_U300_GPIO_PORT3 35 #define IRQ_U300_GPIO_PORT3 36
#define IRQ_U300_GPIO_PORT4 36 #define IRQ_U300_GPIO_PORT4 37
#define IRQ_U300_WDOG 37 #define IRQ_U300_WDOG 38
#define IRQ_U300_EVHIST 38 #define IRQ_U300_EVHIST 39
#define IRQ_U300_MSPRO 39 #define IRQ_U300_MSPRO 40
#define IRQ_U300_MMCSD_MCIINTR0 40 #define IRQ_U300_MMCSD_MCIINTR0 41
#define IRQ_U300_MMCSD_MCIINTR1 41 #define IRQ_U300_MMCSD_MCIINTR1 42
#define IRQ_U300_I2C0 42 #define IRQ_U300_I2C0 43
#define IRQ_U300_I2C1 43 #define IRQ_U300_I2C1 44
#define IRQ_U300_RTC 44 #define IRQ_U300_RTC 45
#define IRQ_U300_NFIF 45 #define IRQ_U300_NFIF 46
#define IRQ_U300_NFIF2 46 #define IRQ_U300_NFIF2 47
#define IRQ_U300_SYSCON_PLL_LOCK 47 #define IRQ_U300_SYSCON_PLL_LOCK 48
#define U300_VIC_IRQS_END 48 #define U300_VIC_IRQS_END 49
#endif #endif
/* Maximum 8*7 GPIO lines */ /* Maximum 8*7 GPIO lines */
...@@ -117,6 +117,6 @@ ...@@ -117,6 +117,6 @@
#define IRQ_U300_GPIO_END (U300_VIC_IRQS_END) #define IRQ_U300_GPIO_END (U300_VIC_IRQS_END)
#endif #endif
#define NR_IRQS (IRQ_U300_GPIO_END) #define NR_IRQS (IRQ_U300_GPIO_END - IRQ_U300_INTCON0_START)
#endif #endif
...@@ -18,6 +18,8 @@ ...@@ -18,6 +18,8 @@
#ifndef __PLAT_S3C_SDHCI_H #ifndef __PLAT_S3C_SDHCI_H
#define __PLAT_S3C_SDHCI_H __FILE__ #define __PLAT_S3C_SDHCI_H __FILE__
#include <plat/devs.h>
struct platform_device; struct platform_device;
struct mmc_host; struct mmc_host;
struct mmc_card; struct mmc_card;
...@@ -356,4 +358,30 @@ static inline void exynos4_default_sdhci3(void) { } ...@@ -356,4 +358,30 @@ static inline void exynos4_default_sdhci3(void) { }
#endif /* CONFIG_EXYNOS4_SETUP_SDHCI */ #endif /* CONFIG_EXYNOS4_SETUP_SDHCI */
static inline void s3c_sdhci_setname(int id, char *name)
{
switch (id) {
#ifdef CONFIG_S3C_DEV_HSMMC
case 0:
s3c_device_hsmmc0.name = name;
break;
#endif
#ifdef CONFIG_S3C_DEV_HSMMC1
case 1:
s3c_device_hsmmc1.name = name;
break;
#endif
#ifdef CONFIG_S3C_DEV_HSMMC2
case 2:
s3c_device_hsmmc2.name = name;
break;
#endif
#ifdef CONFIG_S3C_DEV_HSMMC3
case 3:
s3c_device_hsmmc3.name = name;
break;
#endif
}
}
#endif /* __PLAT_S3C_SDHCI_H */ #endif /* __PLAT_S3C_SDHCI_H */
...@@ -64,6 +64,7 @@ struct pxa_gpio_chip { ...@@ -64,6 +64,7 @@ struct pxa_gpio_chip {
unsigned long irq_mask; unsigned long irq_mask;
unsigned long irq_edge_rise; unsigned long irq_edge_rise;
unsigned long irq_edge_fall; unsigned long irq_edge_fall;
int (*set_wake)(unsigned int gpio, unsigned int on);
#ifdef CONFIG_PM #ifdef CONFIG_PM
unsigned long saved_gplr; unsigned long saved_gplr;
...@@ -269,7 +270,8 @@ static void pxa_gpio_set(struct gpio_chip *chip, unsigned offset, int value) ...@@ -269,7 +270,8 @@ static void pxa_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
(value ? GPSR_OFFSET : GPCR_OFFSET)); (value ? GPSR_OFFSET : GPCR_OFFSET));
} }
static int __devinit pxa_init_gpio_chip(int gpio_end) static int __devinit pxa_init_gpio_chip(int gpio_end,
int (*set_wake)(unsigned int, unsigned int))
{ {
int i, gpio, nbanks = gpio_to_bank(gpio_end) + 1; int i, gpio, nbanks = gpio_to_bank(gpio_end) + 1;
struct pxa_gpio_chip *chips; struct pxa_gpio_chip *chips;
...@@ -285,6 +287,7 @@ static int __devinit pxa_init_gpio_chip(int gpio_end) ...@@ -285,6 +287,7 @@ static int __devinit pxa_init_gpio_chip(int gpio_end)
sprintf(chips[i].label, "gpio-%d", i); sprintf(chips[i].label, "gpio-%d", i);
chips[i].regbase = gpio_reg_base + BANK_OFF(i); chips[i].regbase = gpio_reg_base + BANK_OFF(i);
chips[i].set_wake = set_wake;
c->base = gpio; c->base = gpio;
c->label = chips[i].label; c->label = chips[i].label;
...@@ -412,6 +415,17 @@ static void pxa_mask_muxed_gpio(struct irq_data *d) ...@@ -412,6 +415,17 @@ static void pxa_mask_muxed_gpio(struct irq_data *d)
writel_relaxed(gfer, c->regbase + GFER_OFFSET); writel_relaxed(gfer, c->regbase + GFER_OFFSET);
} }
static int pxa_gpio_set_wake(struct irq_data *d, unsigned int on)
{
int gpio = pxa_irq_to_gpio(d->irq);
struct pxa_gpio_chip *c = gpio_to_pxachip(gpio);
if (c->set_wake)
return c->set_wake(gpio, on);
else
return 0;
}
static void pxa_unmask_muxed_gpio(struct irq_data *d) static void pxa_unmask_muxed_gpio(struct irq_data *d)
{ {
int gpio = pxa_irq_to_gpio(d->irq); int gpio = pxa_irq_to_gpio(d->irq);
...@@ -427,6 +441,7 @@ static struct irq_chip pxa_muxed_gpio_chip = { ...@@ -427,6 +441,7 @@ static struct irq_chip pxa_muxed_gpio_chip = {
.irq_mask = pxa_mask_muxed_gpio, .irq_mask = pxa_mask_muxed_gpio,
.irq_unmask = pxa_unmask_muxed_gpio, .irq_unmask = pxa_unmask_muxed_gpio,
.irq_set_type = pxa_gpio_irq_type, .irq_set_type = pxa_gpio_irq_type,
.irq_set_wake = pxa_gpio_set_wake,
}; };
static int pxa_gpio_nums(void) static int pxa_gpio_nums(void)
...@@ -471,6 +486,7 @@ static int __devinit pxa_gpio_probe(struct platform_device *pdev) ...@@ -471,6 +486,7 @@ static int __devinit pxa_gpio_probe(struct platform_device *pdev)
struct pxa_gpio_chip *c; struct pxa_gpio_chip *c;
struct resource *res; struct resource *res;
struct clk *clk; struct clk *clk;
struct pxa_gpio_platform_data *info;
int gpio, irq, ret; int gpio, irq, ret;
int irq0 = 0, irq1 = 0, irq_mux, gpio_offset = 0; int irq0 = 0, irq1 = 0, irq_mux, gpio_offset = 0;
...@@ -516,7 +532,8 @@ static int __devinit pxa_gpio_probe(struct platform_device *pdev) ...@@ -516,7 +532,8 @@ static int __devinit pxa_gpio_probe(struct platform_device *pdev)
} }
/* Initialize GPIO chips */ /* Initialize GPIO chips */
pxa_init_gpio_chip(pxa_last_gpio); info = dev_get_platdata(&pdev->dev);
pxa_init_gpio_chip(pxa_last_gpio, info ? info->gpio_set_wake : NULL);
/* clear all GPIO edge detects */ /* clear all GPIO edge detects */
for_each_gpio_chip(gpio, c) { for_each_gpio_chip(gpio, c) {
......
...@@ -13,4 +13,8 @@ extern int pxa_last_gpio; ...@@ -13,4 +13,8 @@ extern int pxa_last_gpio;
extern int pxa_irq_to_gpio(int irq); extern int pxa_irq_to_gpio(int irq);
struct pxa_gpio_platform_data {
int (*gpio_set_wake)(unsigned int gpio, unsigned int on);
};
#endif /* __GPIO_PXA_H */ #endif /* __GPIO_PXA_H */
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