Commit b99a9d9b authored by Keith Packard's avatar Keith Packard Committed by Chris Wilson

drm/i915: vblank status not valid while training display port

While the display port is in training mode, vblank interrupts don't
occur. Because we have to wait for the display port output to turn on
before starting the training sequence, enable the output in 'normal'
mode so that we can tell when a vblank has occurred, then start the
training sequence.
Signed-off-by: default avatarKeith Packard <keithp@keithp.com>
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
parent 929f49bf
...@@ -1138,18 +1138,14 @@ static bool ...@@ -1138,18 +1138,14 @@ static bool
intel_dp_set_link_train(struct intel_dp *intel_dp, intel_dp_set_link_train(struct intel_dp *intel_dp,
uint32_t dp_reg_value, uint32_t dp_reg_value,
uint8_t dp_train_pat, uint8_t dp_train_pat,
uint8_t train_set[4], uint8_t train_set[4])
bool first)
{ {
struct drm_device *dev = intel_dp->base.enc.dev; struct drm_device *dev = intel_dp->base.enc.dev;
struct drm_i915_private *dev_priv = dev->dev_private; struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.enc.crtc);
int ret; int ret;
I915_WRITE(intel_dp->output_reg, dp_reg_value); I915_WRITE(intel_dp->output_reg, dp_reg_value);
POSTING_READ(intel_dp->output_reg); POSTING_READ(intel_dp->output_reg);
if (first)
intel_wait_for_vblank(dev, intel_crtc->pipe);
intel_dp_aux_native_write_1(intel_dp, intel_dp_aux_native_write_1(intel_dp,
DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_SET,
...@@ -1174,10 +1170,15 @@ intel_dp_link_train(struct intel_dp *intel_dp) ...@@ -1174,10 +1170,15 @@ intel_dp_link_train(struct intel_dp *intel_dp)
uint8_t voltage; uint8_t voltage;
bool clock_recovery = false; bool clock_recovery = false;
bool channel_eq = false; bool channel_eq = false;
bool first = true;
int tries; int tries;
u32 reg; u32 reg;
uint32_t DP = intel_dp->DP; uint32_t DP = intel_dp->DP;
struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.enc.crtc);
/* Enable output, wait for it to become active */
I915_WRITE(intel_dp->output_reg, intel_dp->DP);
POSTING_READ(intel_dp->output_reg);
intel_wait_for_vblank(dev, intel_crtc->pipe);
/* Write the link configuration data */ /* Write the link configuration data */
intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET, intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
...@@ -1210,9 +1211,8 @@ intel_dp_link_train(struct intel_dp *intel_dp) ...@@ -1210,9 +1211,8 @@ intel_dp_link_train(struct intel_dp *intel_dp)
reg = DP | DP_LINK_TRAIN_PAT_1; reg = DP | DP_LINK_TRAIN_PAT_1;
if (!intel_dp_set_link_train(intel_dp, reg, if (!intel_dp_set_link_train(intel_dp, reg,
DP_TRAINING_PATTERN_1, train_set, first)) DP_TRAINING_PATTERN_1, train_set))
break; break;
first = false;
/* Set training pattern 1 */ /* Set training pattern 1 */
udelay(100); udelay(100);
...@@ -1266,8 +1266,7 @@ intel_dp_link_train(struct intel_dp *intel_dp) ...@@ -1266,8 +1266,7 @@ intel_dp_link_train(struct intel_dp *intel_dp)
/* channel eq pattern */ /* channel eq pattern */
if (!intel_dp_set_link_train(intel_dp, reg, if (!intel_dp_set_link_train(intel_dp, reg,
DP_TRAINING_PATTERN_2, train_set, DP_TRAINING_PATTERN_2, train_set))
false))
break; break;
udelay(400); udelay(400);
......
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