Commit b9bf6a33 authored by Dave Jones's avatar Dave Jones Committed by Dave Jones

[AGPGART] Make AMD64 GART driver marchitecture compliant.

X86_64 -> AMD64
parent 94e7b66d
...@@ -297,11 +297,12 @@ struct agp_bridge_data { ...@@ -297,11 +297,12 @@ struct agp_bridge_data {
#define AMD_TLBFLUSH 0x0c /* In mmio region (32-bit register) */ #define AMD_TLBFLUSH 0x0c /* In mmio region (32-bit register) */
#define AMD_CACHEENTRY 0x10 /* In mmio region (32-bit register) */ #define AMD_CACHEENTRY 0x10 /* In mmio region (32-bit register) */
#define AMD_X86_64_GARTAPERTURECTL 0x90 /* AMD64 registers */
#define AMD_X86_64_GARTAPERTUREBASE 0x94 #define AMD64_GARTAPERTURECTL 0x90
#define AMD_X86_64_GARTTABLEBASE 0x98 #define AMD64_GARTAPERTUREBASE 0x94
#define AMD_X86_64_GARTCACHECTL 0x9c #define AMD64_GARTTABLEBASE 0x98
#define AMD_X86_64_GARTEN 1<<0 #define AMD64_GARTCACHECTL 0x9c
#define AMD64_GARTEN 1<<0
/* ALi registers */ /* ALi registers */
#define ALI_AGPCTRL 0xb8 #define ALI_AGPCTRL 0xb8
......
...@@ -46,9 +46,9 @@ static void flush_x86_64_tlb(struct pci_dev *dev) ...@@ -46,9 +46,9 @@ static void flush_x86_64_tlb(struct pci_dev *dev)
{ {
u32 tmp; u32 tmp;
pci_read_config_dword (dev, AMD_X86_64_GARTCACHECTL, &tmp); pci_read_config_dword (dev, AMD64_GARTCACHECTL, &tmp);
tmp |= INVGART; tmp |= INVGART;
pci_write_config_dword (dev, AMD_X86_64_GARTCACHECTL, tmp); pci_write_config_dword (dev, AMD64_GARTCACHECTL, tmp);
} }
static void amd_x86_64_tlbflush(struct agp_memory *temp) static void amd_x86_64_tlbflush(struct agp_memory *temp)
...@@ -135,7 +135,7 @@ static int amd_x86_64_fetch_size(void) ...@@ -135,7 +135,7 @@ static int amd_x86_64_fetch_size(void)
if (dev==NULL) if (dev==NULL)
return 0; return 0;
pci_read_config_dword(dev, AMD_X86_64_GARTAPERTURECTL, &temp); pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &temp);
temp = (temp & 0xe); temp = (temp & 0xe);
values = A_SIZE_32(x86_64_aperture_sizes); values = A_SIZE_32(x86_64_aperture_sizes);
...@@ -162,7 +162,7 @@ static u64 amd_x86_64_configure (struct pci_dev *hammer, u64 gatt_table) ...@@ -162,7 +162,7 @@ static u64 amd_x86_64_configure (struct pci_dev *hammer, u64 gatt_table)
u64 addr, aper_base; u64 addr, aper_base;
/* Address to map to */ /* Address to map to */
pci_read_config_dword (hammer, AMD_X86_64_GARTAPERTUREBASE, &tmp); pci_read_config_dword (hammer, AMD64_GARTAPERTUREBASE, &tmp);
aperturebase = tmp << 25; aperturebase = tmp << 25;
aper_base = (aperturebase & PCI_BASE_ADDRESS_MEM_MASK); aper_base = (aperturebase & PCI_BASE_ADDRESS_MEM_MASK);
...@@ -171,13 +171,13 @@ static u64 amd_x86_64_configure (struct pci_dev *hammer, u64 gatt_table) ...@@ -171,13 +171,13 @@ static u64 amd_x86_64_configure (struct pci_dev *hammer, u64 gatt_table)
addr >>= 12; addr >>= 12;
tmp = (u32) addr<<4; tmp = (u32) addr<<4;
tmp &= ~0xf; tmp &= ~0xf;
pci_write_config_dword (hammer, AMD_X86_64_GARTTABLEBASE, tmp); pci_write_config_dword (hammer, AMD64_GARTTABLEBASE, tmp);
/* Enable GART translation for this hammer. */ /* Enable GART translation for this hammer. */
pci_read_config_dword(hammer, AMD_X86_64_GARTAPERTURECTL, &tmp); pci_read_config_dword(hammer, AMD64_GARTAPERTURECTL, &tmp);
tmp |= GARTEN; tmp |= GARTEN;
tmp &= ~(DISGARTCPU | DISGARTIO); tmp &= ~(DISGARTCPU | DISGARTIO);
pci_write_config_dword(hammer, AMD_X86_64_GARTAPERTURECTL, tmp); pci_write_config_dword(hammer, AMD64_GARTAPERTURECTL, tmp);
/* keep CPU's coherent. */ /* keep CPU's coherent. */
flush_x86_64_tlb (hammer); flush_x86_64_tlb (hammer);
...@@ -216,9 +216,9 @@ static void amd_8151_cleanup(void) ...@@ -216,9 +216,9 @@ static void amd_8151_cleanup(void)
for_each_nb() { for_each_nb() {
/* disable gart translation */ /* disable gart translation */
pci_read_config_dword (hammers[gart_iterator], AMD_X86_64_GARTAPERTURECTL, &tmp); pci_read_config_dword (hammers[gart_iterator], AMD64_GARTAPERTURECTL, &tmp);
tmp &= ~(AMD_X86_64_GARTEN); tmp &= ~AMD64_GARTEN;
pci_write_config_dword (hammers[gart_iterator], AMD_X86_64_GARTAPERTURECTL, tmp); pci_write_config_dword (hammers[gart_iterator], AMD64_GARTAPERTURECTL, tmp);
} }
} }
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment