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Commit b9eeb512 authored by Vladimir Kondratiev's avatar Vladimir Kondratiev Committed by Kalle Valo
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wil6210: use inline functions for register access 

Replace macros like "R", "W", "S", "C", defined multiple times,
with inline functions "wil_[rwsc]".

Use "readl" and "writel" instead of "ioread32" and "iowrite32"
since it is granted that memory transactions are used,
not port ones like IN/OUT
Signed-off-by: default avatarVladimir Kondratiev <qca_vkondrat@qca.qualcomm.com>
Signed-off-by: default avatarKalle Valo <kvalo@qca.qualcomm.com>
parent bd2d18b5
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Inline Side-by-side
Showing with 151 additions and 170 deletions
drivers/net/wireless/ath/wil6210/debugfs.c
View file @ b9eeb512
...@@ -62,7 +62,7 @@ static void wil_print_vring(struct seq_file *s, struct wil6210_priv *wil, ...@@ -62,7 +62,7 @@ static void wil_print_vring(struct seq_file *s, struct wil6210_priv *wil,
seq_printf(s, " swhead = %d\n", vring->swhead); seq_printf(s, " swhead = %d\n", vring->swhead);
seq_printf(s, " hwtail = [0x%08x] -> ", vring->hwtail); seq_printf(s, " hwtail = [0x%08x] -> ", vring->hwtail);
if (x) { if (x) {
v = ioread32(x); v = readl(x);
seq_printf(s, "0x%08x = %d\n", v, v); seq_printf(s, "0x%08x = %d\n", v, v);
} else { } else {
seq_puts(s, "???\n"); seq_puts(s, "???\n");
...@@ -268,7 +268,7 @@ static const struct file_operations fops_mbox = { ...@@ -268,7 +268,7 @@ static const struct file_operations fops_mbox = {
static int wil_debugfs_iomem_x32_set(void *data, u64 val) static int wil_debugfs_iomem_x32_set(void *data, u64 val)
{ {
iowrite32(val, (void __iomem *)data); writel(val, (void __iomem *)data);
wmb(); /* make sure write propagated to HW */ wmb(); /* make sure write propagated to HW */
return 0; return 0;
...@@ -276,7 +276,7 @@ static int wil_debugfs_iomem_x32_set(void *data, u64 val) ...@@ -276,7 +276,7 @@ static int wil_debugfs_iomem_x32_set(void *data, u64 val)
static int wil_debugfs_iomem_x32_get(void *data, u64 *val) static int wil_debugfs_iomem_x32_get(void *data, u64 *val)
{ {
*val = ioread32((void __iomem *)data); *val = readl((void __iomem *)data);
return 0; return 0;
} }
...@@ -477,7 +477,7 @@ static int wil_memread_debugfs_show(struct seq_file *s, void *data) ...@@ -477,7 +477,7 @@ static int wil_memread_debugfs_show(struct seq_file *s, void *data)
void __iomem *a = wmi_buffer(wil, cpu_to_le32(mem_addr)); void __iomem *a = wmi_buffer(wil, cpu_to_le32(mem_addr));
if (a) if (a)
seq_printf(s, "[0x%08x] = 0x%08x\n", mem_addr, ioread32(a)); seq_printf(s, "[0x%08x] = 0x%08x\n", mem_addr, readl(a));
else else
seq_printf(s, "[0x%08x] = INVALID\n", mem_addr); seq_printf(s, "[0x%08x] = INVALID\n", mem_addr);
......
drivers/net/wireless/ath/wil6210/ethtool.c
View file @ b9eeb512
...@@ -50,19 +50,13 @@ static int wil_ethtoolops_get_coalesce(struct net_device *ndev, ...@@ -50,19 +50,13 @@ static int wil_ethtoolops_get_coalesce(struct net_device *ndev,
wil_dbg_misc(wil, "%s()\n", __func__); wil_dbg_misc(wil, "%s()\n", __func__);
tx_itr_en = ioread32(wil->csr + tx_itr_en = wil_r(wil, RGF_DMA_ITR_TX_CNT_CTL);
HOSTADDR(RGF_DMA_ITR_TX_CNT_CTL));
if (tx_itr_en & BIT_DMA_ITR_TX_CNT_CTL_EN) if (tx_itr_en & BIT_DMA_ITR_TX_CNT_CTL_EN)
tx_itr_val = tx_itr_val = wil_r(wil, RGF_DMA_ITR_TX_CNT_TRSH);
ioread32(wil->csr +
HOSTADDR(RGF_DMA_ITR_TX_CNT_TRSH));
rx_itr_en = ioread32(wil->csr + rx_itr_en = wil_r(wil, RGF_DMA_ITR_RX_CNT_CTL);
HOSTADDR(RGF_DMA_ITR_RX_CNT_CTL));
if (rx_itr_en & BIT_DMA_ITR_RX_CNT_CTL_EN) if (rx_itr_en & BIT_DMA_ITR_RX_CNT_CTL_EN)
rx_itr_val = rx_itr_val = wil_r(wil, RGF_DMA_ITR_RX_CNT_TRSH);
ioread32(wil->csr +
HOSTADDR(RGF_DMA_ITR_RX_CNT_TRSH));
cp->tx_coalesce_usecs = tx_itr_val; cp->tx_coalesce_usecs = tx_itr_val;
cp->rx_coalesce_usecs = rx_itr_val; cp->rx_coalesce_usecs = rx_itr_val;
......
drivers/net/wireless/ath/wil6210/fw.c
View file @ b9eeb512
...@@ -22,16 +22,6 @@ ...@@ -22,16 +22,6 @@
MODULE_FIRMWARE(WIL_FW_NAME); MODULE_FIRMWARE(WIL_FW_NAME);
MODULE_FIRMWARE(WIL_FW2_NAME); MODULE_FIRMWARE(WIL_FW2_NAME);
/* target operations */
/* register read */
#define R(a) ioread32(wil->csr + HOSTADDR(a))
/* register write. wmb() to make sure it is completed */
#define W(a, v) do { iowrite32(v, wil->csr + HOSTADDR(a)); wmb(); } while (0)
/* register set = read, OR, write */
#define S(a, v) W(a, R(a) | v)
/* register clear = read, AND with inverted, write */
#define C(a, v) W(a, R(a) & ~v)
static static
void wil_memset_toio_32(volatile void __iomem *dst, u32 val, void wil_memset_toio_32(volatile void __iomem *dst, u32 val,
size_t count) size_t count)
......
drivers/net/wireless/ath/wil6210/fw_inc.c
View file @ b9eeb512
...@@ -221,12 +221,12 @@ static int fw_handle_direct_write(struct wil6210_priv *wil, const void *data, ...@@ -221,12 +221,12 @@ static int fw_handle_direct_write(struct wil6210_priv *wil, const void *data,
FW_ADDR_CHECK(dst, block[i].addr, "address"); FW_ADDR_CHECK(dst, block[i].addr, "address");
x = ioread32(dst); x = readl(dst);
y = (x & m) | (v & ~m); y = (x & m) | (v & ~m);
wil_dbg_fw(wil, "write [0x%08x] <== 0x%08x " wil_dbg_fw(wil, "write [0x%08x] <== 0x%08x "
"(old 0x%08x val 0x%08x mask 0x%08x)\n", "(old 0x%08x val 0x%08x mask 0x%08x)\n",
le32_to_cpu(block[i].addr), y, x, v, m); le32_to_cpu(block[i].addr), y, x, v, m);
iowrite32(y, dst); writel(y, dst);
wmb(); /* finish before processing next record */ wmb(); /* finish before processing next record */
} }
...@@ -239,18 +239,18 @@ static int gw_write(struct wil6210_priv *wil, void __iomem *gwa_addr, ...@@ -239,18 +239,18 @@ static int gw_write(struct wil6210_priv *wil, void __iomem *gwa_addr,
{ {
unsigned delay = 0; unsigned delay = 0;
iowrite32(a, gwa_addr); writel(a, gwa_addr);
iowrite32(gw_cmd, gwa_cmd); writel(gw_cmd, gwa_cmd);
wmb(); /* finish before activate gw */ wmb(); /* finish before activate gw */
iowrite32(WIL_FW_GW_CTL_RUN, gwa_ctl); /* activate gw */ writel(WIL_FW_GW_CTL_RUN, gwa_ctl); /* activate gw */
do { do {
udelay(1); /* typical time is few usec */ udelay(1); /* typical time is few usec */
if (delay++ > 100) { if (delay++ > 100) {
wil_err_fw(wil, "gw timeout\n"); wil_err_fw(wil, "gw timeout\n");
return -EINVAL; return -EINVAL;
} }
} while (ioread32(gwa_ctl) & WIL_FW_GW_CTL_BUSY); /* gw done? */ } while (readl(gwa_ctl) & WIL_FW_GW_CTL_BUSY); /* gw done? */
return 0; return 0;
} }
...@@ -305,7 +305,7 @@ static int fw_handle_gateway_data(struct wil6210_priv *wil, const void *data, ...@@ -305,7 +305,7 @@ static int fw_handle_gateway_data(struct wil6210_priv *wil, const void *data,
wil_dbg_fw(wil, " gw write[%3d] [0x%08x] <== 0x%08x\n", wil_dbg_fw(wil, " gw write[%3d] [0x%08x] <== 0x%08x\n",
i, a, v); i, a, v);
iowrite32(v, gwa_val); writel(v, gwa_val);
rc = gw_write(wil, gwa_addr, gwa_cmd, gwa_ctl, gw_cmd, a); rc = gw_write(wil, gwa_addr, gwa_cmd, gwa_ctl, gw_cmd, a);
if (rc) if (rc)
return rc; return rc;
...@@ -372,7 +372,7 @@ static int fw_handle_gateway_data4(struct wil6210_priv *wil, const void *data, ...@@ -372,7 +372,7 @@ static int fw_handle_gateway_data4(struct wil6210_priv *wil, const void *data,
sizeof(v), false); sizeof(v), false);
for (k = 0; k < ARRAY_SIZE(block->value); k++) for (k = 0; k < ARRAY_SIZE(block->value); k++)
iowrite32(v[k], gwa_val[k]); writel(v[k], gwa_val[k]);
rc = gw_write(wil, gwa_addr, gwa_cmd, gwa_ctl, gw_cmd, a); rc = gw_write(wil, gwa_addr, gwa_cmd, gwa_ctl, gw_cmd, a);
if (rc) if (rc)
return rc; return rc;
......
drivers/net/wireless/ath/wil6210/interrupt.c
View file @ b9eeb512
...@@ -61,13 +61,13 @@ static inline void wil_icr_clear(u32 x, void __iomem *addr) ...@@ -61,13 +61,13 @@ static inline void wil_icr_clear(u32 x, void __iomem *addr)
static inline void wil_icr_clear(u32 x, void __iomem *addr) static inline void wil_icr_clear(u32 x, void __iomem *addr)
{ {
iowrite32(x, addr); writel(x, addr);
} }
#endif /* defined(CONFIG_WIL6210_ISR_COR) */ #endif /* defined(CONFIG_WIL6210_ISR_COR) */
static inline u32 wil_ioread32_and_clear(void __iomem *addr) static inline u32 wil_ioread32_and_clear(void __iomem *addr)
{ {
u32 x = ioread32(addr); u32 x = readl(addr);
wil_icr_clear(x, addr); wil_icr_clear(x, addr);
...@@ -76,54 +76,47 @@ static inline u32 wil_ioread32_and_clear(void __iomem *addr) ...@@ -76,54 +76,47 @@ static inline u32 wil_ioread32_and_clear(void __iomem *addr)
static void wil6210_mask_irq_tx(struct wil6210_priv *wil) static void wil6210_mask_irq_tx(struct wil6210_priv *wil)
{ {
iowrite32(WIL6210_IRQ_DISABLE, wil->csr + wil_w(wil, RGF_DMA_EP_TX_ICR + offsetof(struct RGF_ICR, IMS),
HOSTADDR(RGF_DMA_EP_TX_ICR) + WIL6210_IRQ_DISABLE);
offsetof(struct RGF_ICR, IMS));
} }
static void wil6210_mask_irq_rx(struct wil6210_priv *wil) static void wil6210_mask_irq_rx(struct wil6210_priv *wil)
{ {
iowrite32(WIL6210_IRQ_DISABLE, wil->csr + wil_w(wil, RGF_DMA_EP_RX_ICR + offsetof(struct RGF_ICR, IMS),
HOSTADDR(RGF_DMA_EP_RX_ICR) + WIL6210_IRQ_DISABLE);
offsetof(struct RGF_ICR, IMS));
} }
static void wil6210_mask_irq_misc(struct wil6210_priv *wil) static void wil6210_mask_irq_misc(struct wil6210_priv *wil)
{ {
iowrite32(WIL6210_IRQ_DISABLE, wil->csr + wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, IMS),
HOSTADDR(RGF_DMA_EP_MISC_ICR) + WIL6210_IRQ_DISABLE);
offsetof(struct RGF_ICR, IMS));
} }
static void wil6210_mask_irq_pseudo(struct wil6210_priv *wil) static void wil6210_mask_irq_pseudo(struct wil6210_priv *wil)
{ {
wil_dbg_irq(wil, "%s()\n", __func__); wil_dbg_irq(wil, "%s()\n", __func__);
iowrite32(WIL6210_IRQ_DISABLE, wil->csr + wil_w(wil, RGF_DMA_PSEUDO_CAUSE_MASK_SW, WIL6210_IRQ_DISABLE);
HOSTADDR(RGF_DMA_PSEUDO_CAUSE_MASK_SW));
clear_bit(wil_status_irqen, wil->status); clear_bit(wil_status_irqen, wil->status);
} }
void wil6210_unmask_irq_tx(struct wil6210_priv *wil) void wil6210_unmask_irq_tx(struct wil6210_priv *wil)
{ {
iowrite32(WIL6210_IMC_TX, wil->csr + wil_w(wil, RGF_DMA_EP_TX_ICR + offsetof(struct RGF_ICR, IMC),
HOSTADDR(RGF_DMA_EP_TX_ICR) + WIL6210_IMC_TX);
offsetof(struct RGF_ICR, IMC));
} }
void wil6210_unmask_irq_rx(struct wil6210_priv *wil) void wil6210_unmask_irq_rx(struct wil6210_priv *wil)
{ {
iowrite32(WIL6210_IMC_RX, wil->csr + wil_w(wil, RGF_DMA_EP_RX_ICR + offsetof(struct RGF_ICR, IMC),
HOSTADDR(RGF_DMA_EP_RX_ICR) + WIL6210_IMC_RX);
offsetof(struct RGF_ICR, IMC));
} }
static void wil6210_unmask_irq_misc(struct wil6210_priv *wil) static void wil6210_unmask_irq_misc(struct wil6210_priv *wil)
{ {
iowrite32(WIL6210_IMC_MISC, wil->csr + wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, IMC),
HOSTADDR(RGF_DMA_EP_MISC_ICR) + WIL6210_IMC_MISC);
offsetof(struct RGF_ICR, IMC));
} }
static void wil6210_unmask_irq_pseudo(struct wil6210_priv *wil) static void wil6210_unmask_irq_pseudo(struct wil6210_priv *wil)
...@@ -132,8 +125,7 @@ static void wil6210_unmask_irq_pseudo(struct wil6210_priv *wil) ...@@ -132,8 +125,7 @@ static void wil6210_unmask_irq_pseudo(struct wil6210_priv *wil)
set_bit(wil_status_irqen, wil->status); set_bit(wil_status_irqen, wil->status);
iowrite32(WIL6210_IRQ_PSEUDO_MASK, wil->csr + wil_w(wil, RGF_DMA_PSEUDO_CAUSE_MASK_SW, WIL6210_IRQ_PSEUDO_MASK);
HOSTADDR(RGF_DMA_PSEUDO_CAUSE_MASK_SW));
} }
void wil_mask_irq(struct wil6210_priv *wil) void wil_mask_irq(struct wil6210_priv *wil)
...@@ -150,12 +142,12 @@ void wil_unmask_irq(struct wil6210_priv *wil) ...@@ -150,12 +142,12 @@ void wil_unmask_irq(struct wil6210_priv *wil)
{ {
wil_dbg_irq(wil, "%s()\n", __func__); wil_dbg_irq(wil, "%s()\n", __func__);
iowrite32(WIL_ICR_ICC_VALUE, wil->csr + HOSTADDR(RGF_DMA_EP_RX_ICR) + wil_w(wil, RGF_DMA_EP_RX_ICR + offsetof(struct RGF_ICR, ICC),
offsetof(struct RGF_ICR, ICC)); WIL_ICR_ICC_VALUE);
iowrite32(WIL_ICR_ICC_VALUE, wil->csr + HOSTADDR(RGF_DMA_EP_TX_ICR) + wil_w(wil, RGF_DMA_EP_TX_ICR + offsetof(struct RGF_ICR, ICC),
offsetof(struct RGF_ICR, ICC)); WIL_ICR_ICC_VALUE);
iowrite32(WIL_ICR_ICC_VALUE, wil->csr + HOSTADDR(RGF_DMA_EP_MISC_ICR) + wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, ICC),
offsetof(struct RGF_ICR, ICC)); WIL_ICR_ICC_VALUE);
wil6210_unmask_irq_pseudo(wil); wil6210_unmask_irq_pseudo(wil);
wil6210_unmask_irq_tx(wil); wil6210_unmask_irq_tx(wil);
...@@ -163,9 +155,6 @@ void wil_unmask_irq(struct wil6210_priv *wil) ...@@ -163,9 +155,6 @@ void wil_unmask_irq(struct wil6210_priv *wil)
wil6210_unmask_irq_misc(wil); wil6210_unmask_irq_misc(wil);
} }
/* target write operation */
#define W(a, v) do { iowrite32(v, wil->csr + HOSTADDR(a)); wmb(); } while (0)
void wil_configure_interrupt_moderation(struct wil6210_priv *wil) void wil_configure_interrupt_moderation(struct wil6210_priv *wil)
{ {
wil_dbg_irq(wil, "%s()\n", __func__); wil_dbg_irq(wil, "%s()\n", __func__);
...@@ -177,44 +166,42 @@ void wil_configure_interrupt_moderation(struct wil6210_priv *wil) ...@@ -177,44 +166,42 @@ void wil_configure_interrupt_moderation(struct wil6210_priv *wil)
return; return;
/* Disable and clear tx counter before (re)configuration */ /* Disable and clear tx counter before (re)configuration */
W(RGF_DMA_ITR_TX_CNT_CTL, BIT_DMA_ITR_TX_CNT_CTL_CLR); wil_w(wil, RGF_DMA_ITR_TX_CNT_CTL, BIT_DMA_ITR_TX_CNT_CTL_CLR);
W(RGF_DMA_ITR_TX_CNT_TRSH, wil->tx_max_burst_duration); wil_w(wil, RGF_DMA_ITR_TX_CNT_TRSH, wil->tx_max_burst_duration);
wil_info(wil, "set ITR_TX_CNT_TRSH = %d usec\n", wil_info(wil, "set ITR_TX_CNT_TRSH = %d usec\n",
wil->tx_max_burst_duration); wil->tx_max_burst_duration);
/* Configure TX max burst duration timer to use usec units */ /* Configure TX max burst duration timer to use usec units */
W(RGF_DMA_ITR_TX_CNT_CTL, wil_w(wil, RGF_DMA_ITR_TX_CNT_CTL,
BIT_DMA_ITR_TX_CNT_CTL_EN | BIT_DMA_ITR_TX_CNT_CTL_EXT_TIC_SEL); BIT_DMA_ITR_TX_CNT_CTL_EN | BIT_DMA_ITR_TX_CNT_CTL_EXT_TIC_SEL);
/* Disable and clear tx idle counter before (re)configuration */ /* Disable and clear tx idle counter before (re)configuration */
W(RGF_DMA_ITR_TX_IDL_CNT_CTL, BIT_DMA_ITR_TX_IDL_CNT_CTL_CLR); wil_w(wil, RGF_DMA_ITR_TX_IDL_CNT_CTL, BIT_DMA_ITR_TX_IDL_CNT_CTL_CLR);
W(RGF_DMA_ITR_TX_IDL_CNT_TRSH, wil->tx_interframe_timeout); wil_w(wil, RGF_DMA_ITR_TX_IDL_CNT_TRSH, wil->tx_interframe_timeout);
wil_info(wil, "set ITR_TX_IDL_CNT_TRSH = %d usec\n", wil_info(wil, "set ITR_TX_IDL_CNT_TRSH = %d usec\n",
wil->tx_interframe_timeout); wil->tx_interframe_timeout);
/* Configure TX max burst duration timer to use usec units */ /* Configure TX max burst duration timer to use usec units */
W(RGF_DMA_ITR_TX_IDL_CNT_CTL, BIT_DMA_ITR_TX_IDL_CNT_CTL_EN | wil_w(wil, RGF_DMA_ITR_TX_IDL_CNT_CTL, BIT_DMA_ITR_TX_IDL_CNT_CTL_EN |
BIT_DMA_ITR_TX_IDL_CNT_CTL_EXT_TIC_SEL); BIT_DMA_ITR_TX_IDL_CNT_CTL_EXT_TIC_SEL);
/* Disable and clear rx counter before (re)configuration */ /* Disable and clear rx counter before (re)configuration */
W(RGF_DMA_ITR_RX_CNT_CTL, BIT_DMA_ITR_RX_CNT_CTL_CLR); wil_w(wil, RGF_DMA_ITR_RX_CNT_CTL, BIT_DMA_ITR_RX_CNT_CTL_CLR);
W(RGF_DMA_ITR_RX_CNT_TRSH, wil->rx_max_burst_duration); wil_w(wil, RGF_DMA_ITR_RX_CNT_TRSH, wil->rx_max_burst_duration);
wil_info(wil, "set ITR_RX_CNT_TRSH = %d usec\n", wil_info(wil, "set ITR_RX_CNT_TRSH = %d usec\n",
wil->rx_max_burst_duration); wil->rx_max_burst_duration);
/* Configure TX max burst duration timer to use usec units */ /* Configure TX max burst duration timer to use usec units */
W(RGF_DMA_ITR_RX_CNT_CTL, wil_w(wil, RGF_DMA_ITR_RX_CNT_CTL,
BIT_DMA_ITR_RX_CNT_CTL_EN | BIT_DMA_ITR_RX_CNT_CTL_EXT_TIC_SEL); BIT_DMA_ITR_RX_CNT_CTL_EN | BIT_DMA_ITR_RX_CNT_CTL_EXT_TIC_SEL);
/* Disable and clear rx idle counter before (re)configuration */ /* Disable and clear rx idle counter before (re)configuration */
W(RGF_DMA_ITR_RX_IDL_CNT_CTL, BIT_DMA_ITR_RX_IDL_CNT_CTL_CLR); wil_w(wil, RGF_DMA_ITR_RX_IDL_CNT_CTL, BIT_DMA_ITR_RX_IDL_CNT_CTL_CLR);
W(RGF_DMA_ITR_RX_IDL_CNT_TRSH, wil->rx_interframe_timeout); wil_w(wil, RGF_DMA_ITR_RX_IDL_CNT_TRSH, wil->rx_interframe_timeout);
wil_info(wil, "set ITR_RX_IDL_CNT_TRSH = %d usec\n", wil_info(wil, "set ITR_RX_IDL_CNT_TRSH = %d usec\n",
wil->rx_interframe_timeout); wil->rx_interframe_timeout);
/* Configure TX max burst duration timer to use usec units */ /* Configure TX max burst duration timer to use usec units */
W(RGF_DMA_ITR_RX_IDL_CNT_CTL, BIT_DMA_ITR_RX_IDL_CNT_CTL_EN | wil_w(wil, RGF_DMA_ITR_RX_IDL_CNT_CTL, BIT_DMA_ITR_RX_IDL_CNT_CTL_EN |
BIT_DMA_ITR_RX_IDL_CNT_CTL_EXT_TIC_SEL); BIT_DMA_ITR_RX_IDL_CNT_CTL_EXT_TIC_SEL);
} }
#undef W
static irqreturn_t wil6210_irq_rx(int irq, void *cookie) static irqreturn_t wil6210_irq_rx(int irq, void *cookie)
{ {
struct wil6210_priv *wil = cookie; struct wil6210_priv *wil = cookie;
...@@ -452,27 +439,24 @@ static int wil6210_debug_irq_mask(struct wil6210_priv *wil, u32 pseudo_cause) ...@@ -452,27 +439,24 @@ static int wil6210_debug_irq_mask(struct wil6210_priv *wil, u32 pseudo_cause)
u32 icr_rx = wil_ioread32_and_clear(wil->csr + u32 icr_rx = wil_ioread32_and_clear(wil->csr +
HOSTADDR(RGF_DMA_EP_RX_ICR) + HOSTADDR(RGF_DMA_EP_RX_ICR) +
offsetof(struct RGF_ICR, ICR)); offsetof(struct RGF_ICR, ICR));
u32 imv_rx = ioread32(wil->csr + u32 imv_rx = wil_r(wil, RGF_DMA_EP_RX_ICR +
HOSTADDR(RGF_DMA_EP_RX_ICR) + offsetof(struct RGF_ICR, IMV));
offsetof(struct RGF_ICR, IMV));
u32 icm_tx = wil_ioread32_and_clear(wil->csr + u32 icm_tx = wil_ioread32_and_clear(wil->csr +
HOSTADDR(RGF_DMA_EP_TX_ICR) + HOSTADDR(RGF_DMA_EP_TX_ICR) +
offsetof(struct RGF_ICR, ICM)); offsetof(struct RGF_ICR, ICM));
u32 icr_tx = wil_ioread32_and_clear(wil->csr + u32 icr_tx = wil_ioread32_and_clear(wil->csr +
HOSTADDR(RGF_DMA_EP_TX_ICR) + HOSTADDR(RGF_DMA_EP_TX_ICR) +
offsetof(struct RGF_ICR, ICR)); offsetof(struct RGF_ICR, ICR));
u32 imv_tx = ioread32(wil->csr + u32 imv_tx = wil_r(wil, RGF_DMA_EP_TX_ICR +
HOSTADDR(RGF_DMA_EP_TX_ICR) + offsetof(struct RGF_ICR, IMV));
offsetof(struct RGF_ICR, IMV));
u32 icm_misc = wil_ioread32_and_clear(wil->csr + u32 icm_misc = wil_ioread32_and_clear(wil->csr +
HOSTADDR(RGF_DMA_EP_MISC_ICR) + HOSTADDR(RGF_DMA_EP_MISC_ICR) +
offsetof(struct RGF_ICR, ICM)); offsetof(struct RGF_ICR, ICM));
u32 icr_misc = wil_ioread32_and_clear(wil->csr + u32 icr_misc = wil_ioread32_and_clear(wil->csr +
HOSTADDR(RGF_DMA_EP_MISC_ICR) + HOSTADDR(RGF_DMA_EP_MISC_ICR) +
offsetof(struct RGF_ICR, ICR)); offsetof(struct RGF_ICR, ICR));
u32 imv_misc = ioread32(wil->csr + u32 imv_misc = wil_r(wil, RGF_DMA_EP_MISC_ICR +
HOSTADDR(RGF_DMA_EP_MISC_ICR) + offsetof(struct RGF_ICR, IMV));
offsetof(struct RGF_ICR, IMV));
wil_err(wil, "IRQ when it should be masked: pseudo 0x%08x\n" wil_err(wil, "IRQ when it should be masked: pseudo 0x%08x\n"
"Rx icm:icr:imv 0x%08x 0x%08x 0x%08x\n" "Rx icm:icr:imv 0x%08x 0x%08x 0x%08x\n"
"Tx icm:icr:imv 0x%08x 0x%08x 0x%08x\n" "Tx icm:icr:imv 0x%08x 0x%08x 0x%08x\n"
...@@ -492,7 +476,7 @@ static irqreturn_t wil6210_hardirq(int irq, void *cookie) ...@@ -492,7 +476,7 @@ static irqreturn_t wil6210_hardirq(int irq, void *cookie)
{ {
irqreturn_t rc = IRQ_HANDLED; irqreturn_t rc = IRQ_HANDLED;
struct wil6210_priv *wil = cookie; struct wil6210_priv *wil = cookie;
u32 pseudo_cause = ioread32(wil->csr + HOSTADDR(RGF_DMA_PSEUDO_CAUSE)); u32 pseudo_cause = wil_r(wil, RGF_DMA_PSEUDO_CAUSE);
/** /**
* pseudo_cause is Clear-On-Read, no need to ACK * pseudo_cause is Clear-On-Read, no need to ACK
...@@ -544,9 +528,9 @@ static irqreturn_t wil6210_hardirq(int irq, void *cookie) ...@@ -544,9 +528,9 @@ static irqreturn_t wil6210_hardirq(int irq, void *cookie)
/* can't use wil_ioread32_and_clear because ICC value is not set yet */ /* can't use wil_ioread32_and_clear because ICC value is not set yet */
static inline void wil_clear32(void __iomem *addr) static inline void wil_clear32(void __iomem *addr)
{ {
u32 x = ioread32(addr); u32 x = readl(addr);
iowrite32(x, addr); writel(x, addr);
} }
void wil6210_clear_irq(struct wil6210_priv *wil) void wil6210_clear_irq(struct wil6210_priv *wil)
......
drivers/net/wireless/ath/wil6210/ioctl.c
View file @ b9eeb512
...@@ -76,11 +76,11 @@ static int wil_ioc_memio_dword(struct wil6210_priv *wil, void __user *data) ...@@ -76,11 +76,11 @@ static int wil_ioc_memio_dword(struct wil6210_priv *wil, void __user *data)
/* operation */ /* operation */
switch (io.op & wil_mmio_op_mask) { switch (io.op & wil_mmio_op_mask) {
case wil_mmio_read: case wil_mmio_read:
io.val = ioread32(a); io.val = readl(a);
need_copy = true; need_copy = true;
break; break;
case wil_mmio_write: case wil_mmio_write:
iowrite32(io.val, a); writel(io.val, a);
wmb(); /* make sure write propagated to HW */ wmb(); /* make sure write propagated to HW */
break; break;
default: default:
......
drivers/net/wireless/ath/wil6210/main.c
View file @ b9eeb512
...@@ -528,26 +528,16 @@ void wil_priv_deinit(struct wil6210_priv *wil) ...@@ -528,26 +528,16 @@ void wil_priv_deinit(struct wil6210_priv *wil)
destroy_workqueue(wil->wmi_wq); destroy_workqueue(wil->wmi_wq);
} }
/* target operations */
/* register read */
#define R(a) ioread32(wil->csr + HOSTADDR(a))
/* register write. wmb() to make sure it is completed */
#define W(a, v) do { iowrite32(v, wil->csr + HOSTADDR(a)); wmb(); } while (0)
/* register set = read, OR, write */
#define S(a, v) W(a, R(a) | v)
/* register clear = read, AND with inverted, write */
#define C(a, v) W(a, R(a) & ~v)
static inline void wil_halt_cpu(struct wil6210_priv *wil) static inline void wil_halt_cpu(struct wil6210_priv *wil)
{ {
W(RGF_USER_USER_CPU_0, BIT_USER_USER_CPU_MAN_RST); wil_w(wil, RGF_USER_USER_CPU_0, BIT_USER_USER_CPU_MAN_RST);
W(RGF_USER_MAC_CPU_0, BIT_USER_MAC_CPU_MAN_RST); wil_w(wil, RGF_USER_MAC_CPU_0, BIT_USER_MAC_CPU_MAN_RST);
} }
static inline void wil_release_cpu(struct wil6210_priv *wil) static inline void wil_release_cpu(struct wil6210_priv *wil)
{ {
/* Start CPU */ /* Start CPU */
W(RGF_USER_USER_CPU_0, 1); wil_w(wil, RGF_USER_USER_CPU_0, 1);
} }
static int wil_target_reset(struct wil6210_priv *wil) static int wil_target_reset(struct wil6210_priv *wil)
...@@ -558,58 +548,60 @@ static int wil_target_reset(struct wil6210_priv *wil) ...@@ -558,58 +548,60 @@ static int wil_target_reset(struct wil6210_priv *wil)
wil_dbg_misc(wil, "Resetting \"%s\"...\n", wil->hw_name); wil_dbg_misc(wil, "Resetting \"%s\"...\n", wil->hw_name);
/* Clear MAC link up */ /* Clear MAC link up */
S(RGF_HP_CTRL, BIT(15)); wil_s(wil, RGF_HP_CTRL, BIT(15));
S(RGF_USER_CLKS_CTL_SW_RST_MASK_0, BIT_HPAL_PERST_FROM_PAD); wil_s(wil, RGF_USER_CLKS_CTL_SW_RST_MASK_0, BIT_HPAL_PERST_FROM_PAD);
S(RGF_USER_CLKS_CTL_SW_RST_MASK_0, BIT_CAR_PERST_RST); wil_s(wil, RGF_USER_CLKS_CTL_SW_RST_MASK_0, BIT_CAR_PERST_RST);
wil_halt_cpu(wil); wil_halt_cpu(wil);
/* clear all boot loader "ready" bits */ /* clear all boot loader "ready" bits */
W(RGF_USER_BL + wil_w(wil, RGF_USER_BL +
offsetof(struct bl_dedicated_registers_v0, boot_loader_ready), 0); offsetof(struct bl_dedicated_registers_v0, boot_loader_ready), 0);
/* Clear Fw Download notification */ /* Clear Fw Download notification */
C(RGF_USER_USAGE_6, BIT(0)); wil_c(wil, RGF_USER_USAGE_6, BIT(0));
S(RGF_CAF_OSC_CONTROL, BIT_CAF_OSC_XTAL_EN); wil_s(wil, RGF_CAF_OSC_CONTROL, BIT_CAF_OSC_XTAL_EN);
/* XTAL stabilization should take about 3ms */ /* XTAL stabilization should take about 3ms */
usleep_range(5000, 7000); usleep_range(5000, 7000);
x = R(RGF_CAF_PLL_LOCK_STATUS); x = wil_r(wil, RGF_CAF_PLL_LOCK_STATUS);
if (!(x & BIT_CAF_OSC_DIG_XTAL_STABLE)) { if (!(x & BIT_CAF_OSC_DIG_XTAL_STABLE)) {
wil_err(wil, "Xtal stabilization timeout\n" wil_err(wil, "Xtal stabilization timeout\n"
"RGF_CAF_PLL_LOCK_STATUS = 0x%08x\n", x); "RGF_CAF_PLL_LOCK_STATUS = 0x%08x\n", x);
return -ETIME; return -ETIME;
} }
/* switch 10k to XTAL*/ /* switch 10k to XTAL*/
C(RGF_USER_SPARROW_M_4, BIT_SPARROW_M_4_SEL_SLEEP_OR_REF); wil_c(wil, RGF_USER_SPARROW_M_4, BIT_SPARROW_M_4_SEL_SLEEP_OR_REF);
/* 40 MHz */ /* 40 MHz */
C(RGF_USER_CLKS_CTL_0, BIT_USER_CLKS_CAR_AHB_SW_SEL); wil_c(wil, RGF_USER_CLKS_CTL_0, BIT_USER_CLKS_CAR_AHB_SW_SEL);
W(RGF_USER_CLKS_CTL_EXT_SW_RST_VEC_0, 0x3ff81f); wil_w(wil, RGF_USER_CLKS_CTL_EXT_SW_RST_VEC_0, 0x3ff81f);
W(RGF_USER_CLKS_CTL_EXT_SW_RST_VEC_1, 0xf); wil_w(wil, RGF_USER_CLKS_CTL_EXT_SW_RST_VEC_1, 0xf);
W(RGF_USER_CLKS_CTL_SW_RST_VEC_2, 0xFE000000); wil_w(wil, RGF_USER_CLKS_CTL_SW_RST_VEC_2, 0xFE000000);
W(RGF_USER_CLKS_CTL_SW_RST_VEC_1, 0x0000003F); wil_w(wil, RGF_USER_CLKS_CTL_SW_RST_VEC_1, 0x0000003F);
W(RGF_USER_CLKS_CTL_SW_RST_VEC_3, 0x000000f0); wil_w(wil, RGF_USER_CLKS_CTL_SW_RST_VEC_3, 0x000000f0);
W(RGF_USER_CLKS_CTL_SW_RST_VEC_0, 0xFFE7FE00); wil_w(wil, RGF_USER_CLKS_CTL_SW_RST_VEC_0, 0xFFE7FE00);
W(RGF_USER_CLKS_CTL_EXT_SW_RST_VEC_0, 0x0); wil_w(wil, RGF_USER_CLKS_CTL_EXT_SW_RST_VEC_0, 0x0);
W(RGF_USER_CLKS_CTL_EXT_SW_RST_VEC_1, 0x0); wil_w(wil, RGF_USER_CLKS_CTL_EXT_SW_RST_VEC_1, 0x0);
W(RGF_USER_CLKS_CTL_SW_RST_VEC_3, 0); wil_w(wil, RGF_USER_CLKS_CTL_SW_RST_VEC_3, 0);
W(RGF_USER_CLKS_CTL_SW_RST_VEC_2, 0); wil_w(wil, RGF_USER_CLKS_CTL_SW_RST_VEC_2, 0);
W(RGF_USER_CLKS_CTL_SW_RST_VEC_1, 0); wil_w(wil, RGF_USER_CLKS_CTL_SW_RST_VEC_1, 0);
W(RGF_USER_CLKS_CTL_SW_RST_VEC_0, 0); wil_w(wil, RGF_USER_CLKS_CTL_SW_RST_VEC_0, 0);
W(RGF_USER_CLKS_CTL_SW_RST_VEC_3, 0x00000003); wil_w(wil, RGF_USER_CLKS_CTL_SW_RST_VEC_3, 0x00000003);
W(RGF_USER_CLKS_CTL_SW_RST_VEC_2, 0x00008000); /* reset A2 PCIE AHB */ /* reset A2 PCIE AHB */
wil_w(wil, RGF_USER_CLKS_CTL_SW_RST_VEC_2, 0x00008000);
W(RGF_USER_CLKS_CTL_SW_RST_VEC_0, 0); wil_w(wil, RGF_USER_CLKS_CTL_SW_RST_VEC_0, 0);
/* wait until device ready. typical time is 20..80 msec */ /* wait until device ready. typical time is 20..80 msec */
do { do {
msleep(RST_DELAY); msleep(RST_DELAY);
x = R(RGF_USER_BL + offsetof(struct bl_dedicated_registers_v0, x = wil_r(wil, RGF_USER_BL +
boot_loader_ready)); offsetof(struct bl_dedicated_registers_v0,
boot_loader_ready));
if (x1 != x) { if (x1 != x) {
wil_dbg_misc(wil, "BL.ready 0x%08x => 0x%08x\n", x1, x); wil_dbg_misc(wil, "BL.ready 0x%08x => 0x%08x\n", x1, x);
x1 = x; x1 = x;
...@@ -621,11 +613,11 @@ static int wil_target_reset(struct wil6210_priv *wil) ...@@ -621,11 +613,11 @@ static int wil_target_reset(struct wil6210_priv *wil)
} }
} while (x != BL_READY); } while (x != BL_READY);
C(RGF_USER_CLKS_CTL_0, BIT_USER_CLKS_RST_PWGD); wil_c(wil, RGF_USER_CLKS_CTL_0, BIT_USER_CLKS_RST_PWGD);
/* enable fix for HW bug related to the SA/DA swap in AP Rx */ /* enable fix for HW bug related to the SA/DA swap in AP Rx */
S(RGF_DMA_OFUL_NID_0, BIT_DMA_OFUL_NID_0_RX_EXT_TR_EN | wil_s(wil, RGF_DMA_OFUL_NID_0, BIT_DMA_OFUL_NID_0_RX_EXT_TR_EN |
BIT_DMA_OFUL_NID_0_RX_EXT_A3_SRC); BIT_DMA_OFUL_NID_0_RX_EXT_A3_SRC);
wil_dbg_misc(wil, "Reset completed in %d ms\n", delay * RST_DELAY); wil_dbg_misc(wil, "Reset completed in %d ms\n", delay * RST_DELAY);
return 0; return 0;
...@@ -651,8 +643,9 @@ static int wil_get_bl_info(struct wil6210_priv *wil) ...@@ -651,8 +643,9 @@ static int wil_get_bl_info(struct wil6210_priv *wil)
u8 *mac; u8 *mac;
u16 rf_status; u16 rf_status;
bl_ver = R(RGF_USER_BL + offsetof(struct bl_dedicated_registers_v0, bl_ver = wil_r(wil, RGF_USER_BL +
boot_loader_struct_version)); offsetof(struct bl_dedicated_registers_v0,
boot_loader_struct_version));
switch (bl_ver) { switch (bl_ver) {
case 0: case 0:
wil_memcpy_fromio_32(&bl, wil->csr + HOSTADDR(RGF_USER_BL), wil_memcpy_fromio_32(&bl, wil->csr + HOSTADDR(RGF_USER_BL),
...@@ -802,7 +795,7 @@ int wil_reset(struct wil6210_priv *wil, bool load_fw) ...@@ -802,7 +795,7 @@ int wil_reset(struct wil6210_priv *wil, bool load_fw)
return rc; return rc;
/* Mark FW as loaded from host */ /* Mark FW as loaded from host */
S(RGF_USER_USAGE_6, 1); wil_s(wil, RGF_USER_USAGE_6, 1);
/* clear any interrupts which on-card-firmware /* clear any interrupts which on-card-firmware
* may have set * may have set
...@@ -810,8 +803,8 @@ int wil_reset(struct wil6210_priv *wil, bool load_fw) ...@@ -810,8 +803,8 @@ int wil_reset(struct wil6210_priv *wil, bool load_fw)
wil6210_clear_irq(wil); wil6210_clear_irq(wil);
/* CAF_ICR - clear and mask */ /* CAF_ICR - clear and mask */
/* it is W1C, clear by writing back same value */ /* it is W1C, clear by writing back same value */
S(RGF_CAF_ICR + offsetof(struct RGF_ICR, ICR), 0); wil_s(wil, RGF_CAF_ICR + offsetof(struct RGF_ICR, ICR), 0);
W(RGF_CAF_ICR + offsetof(struct RGF_ICR, IMV), ~0); wil_w(wil, RGF_CAF_ICR + offsetof(struct RGF_ICR, IMV), ~0);
wil_release_cpu(wil); wil_release_cpu(wil);
} }
...@@ -835,11 +828,6 @@ int wil_reset(struct wil6210_priv *wil, bool load_fw) ...@@ -835,11 +828,6 @@ int wil_reset(struct wil6210_priv *wil, bool load_fw)
return rc; return rc;
} }
#undef R
#undef W
#undef S
#undef C
void wil_fw_error_recovery(struct wil6210_priv *wil) void wil_fw_error_recovery(struct wil6210_priv *wil)
{ {
wil_dbg_misc(wil, "starting fw error recovery\n"); wil_dbg_misc(wil, "starting fw error recovery\n");
......
drivers/net/wireless/ath/wil6210/pcie_bus.c
View file @ b9eeb512
...@@ -28,7 +28,7 @@ MODULE_PARM_DESC(use_msi, " Use MSI interrupt, default - true"); ...@@ -28,7 +28,7 @@ MODULE_PARM_DESC(use_msi, " Use MSI interrupt, default - true");
static static
void wil_set_capabilities(struct wil6210_priv *wil) void wil_set_capabilities(struct wil6210_priv *wil)
{ {
u32 rev_id = ioread32(wil->csr + HOSTADDR(RGF_USER_JTAG_DEV_ID)); u32 rev_id = wil_r(wil, RGF_USER_JTAG_DEV_ID);
bitmap_zero(wil->hw_capabilities, hw_capability_last); bitmap_zero(wil->hw_capabilities, hw_capability_last);
......
drivers/net/wireless/ath/wil6210/txrx.c
View file @ b9eeb512
...@@ -509,7 +509,7 @@ static int wil_rx_refill(struct wil6210_priv *wil, int count) ...@@ -509,7 +509,7 @@ static int wil_rx_refill(struct wil6210_priv *wil, int count)
break; break;
} }
} }
iowrite32(v->swtail, wil->csr + HOSTADDR(v->hwtail)); wil_w(wil, v->hwtail, v->swtail);
return rc; return rc;
} }
...@@ -1422,7 +1422,7 @@ static int __wil_tx_vring_tso(struct wil6210_priv *wil, struct vring *vring, ...@@ -1422,7 +1422,7 @@ static int __wil_tx_vring_tso(struct wil6210_priv *wil, struct vring *vring,
*/ */
wmb(); wmb();
iowrite32(vring->swhead, wil->csr + HOSTADDR(vring->hwtail)); wil_w(wil, vring->hwtail, vring->swhead);
return 0; return 0;
dma_error: dma_error:
...@@ -1565,7 +1565,7 @@ static int __wil_tx_vring(struct wil6210_priv *wil, struct vring *vring, ...@@ -1565,7 +1565,7 @@ static int __wil_tx_vring(struct wil6210_priv *wil, struct vring *vring,
*/ */
wmb(); wmb();
iowrite32(vring->swhead, wil->csr + HOSTADDR(vring->hwtail)); wil_w(wil, vring->hwtail, vring->swhead);
return 0; return 0;
dma_error: dma_error:
......
drivers/net/wireless/ath/wil6210/wil6210.h
View file @ b9eeb512
...@@ -252,9 +252,8 @@ enum { ...@@ -252,9 +252,8 @@ enum {
}; };
/* popular locations */ /* popular locations */
#define HOST_MBOX HOSTADDR(RGF_USER_USER_SCRATCH_PAD) #define RGF_MBOX RGF_USER_USER_SCRATCH_PAD
#define HOST_SW_INT (HOSTADDR(RGF_USER_USER_ICR) + \ #define HOST_MBOX HOSTADDR(RGF_MBOX)
offsetof(struct RGF_ICR, ICS))
#define SW_INT_MBOX BIT_USER_USER_ICR_SW_INT_2 #define SW_INT_MBOX BIT_USER_USER_ICR_SW_INT_2
/* ISR register bits */ /* ISR register bits */
...@@ -649,6 +648,32 @@ void wil_info(struct wil6210_priv *wil, const char *fmt, ...); ...@@ -649,6 +648,32 @@ void wil_info(struct wil6210_priv *wil, const char *fmt, ...);
#define wil_dbg_wmi(wil, fmt, arg...) wil_dbg(wil, "DBG[ WMI]" fmt, ##arg) #define wil_dbg_wmi(wil, fmt, arg...) wil_dbg(wil, "DBG[ WMI]" fmt, ##arg)
#define wil_dbg_misc(wil, fmt, arg...) wil_dbg(wil, "DBG[MISC]" fmt, ##arg) #define wil_dbg_misc(wil, fmt, arg...) wil_dbg(wil, "DBG[MISC]" fmt, ##arg)
/* target operations */
/* register read */
static inline u32 wil_r(struct wil6210_priv *wil, u32 reg)
{
return readl(wil->csr + HOSTADDR(reg));
}
/* register write. wmb() to make sure it is completed */
static inline void wil_w(struct wil6210_priv *wil, u32 reg, u32 val)
{
writel(val, wil->csr + HOSTADDR(reg));
wmb(); /* wait for write to propagate to the HW */
}
/* register set = read, OR, write */
static inline void wil_s(struct wil6210_priv *wil, u32 reg, u32 val)
{
wil_w(wil, reg, wil_r(wil, reg) | val);
}
/* register clear = read, AND with inverted, write */
static inline void wil_c(struct wil6210_priv *wil, u32 reg, u32 val)
{
wil_w(wil, reg, wil_r(wil, reg) & ~val);
}
#if defined(CONFIG_DYNAMIC_DEBUG) #if defined(CONFIG_DYNAMIC_DEBUG)
#define wil_hex_dump_txrx(prefix_str, prefix_type, rowsize, \ #define wil_hex_dump_txrx(prefix_str, prefix_type, rowsize, \
groupsize, buf, len, ascii) \ groupsize, buf, len, ascii) \
......
drivers/net/wireless/ath/wil6210/wmi.c
View file @ b9eeb512
...@@ -228,8 +228,8 @@ static int __wmi_send(struct wil6210_priv *wil, u16 cmdid, void *buf, u16 len) ...@@ -228,8 +228,8 @@ static int __wmi_send(struct wil6210_priv *wil, u16 cmdid, void *buf, u16 len)
wil_dbg_wmi(wil, "Head 0x%08x -> 0x%08x\n", r->head, next_head); wil_dbg_wmi(wil, "Head 0x%08x -> 0x%08x\n", r->head, next_head);
/* wait till FW finish with previous command */ /* wait till FW finish with previous command */
for (retry = 5; retry > 0; retry--) { for (retry = 5; retry > 0; retry--) {
r->tail = ioread32(wil->csr + HOST_MBOX + r->tail = wil_r(wil, RGF_MBOX +
offsetof(struct wil6210_mbox_ctl, tx.tail)); offsetof(struct wil6210_mbox_ctl, tx.tail));
if (next_head != r->tail) if (next_head != r->tail)
break; break;
msleep(20); msleep(20);
...@@ -254,16 +254,16 @@ static int __wmi_send(struct wil6210_priv *wil, u16 cmdid, void *buf, u16 len) ...@@ -254,16 +254,16 @@ static int __wmi_send(struct wil6210_priv *wil, u16 cmdid, void *buf, u16 len)
wil_memcpy_toio_32(dst, &cmd, sizeof(cmd)); wil_memcpy_toio_32(dst, &cmd, sizeof(cmd));
wil_memcpy_toio_32(dst + sizeof(cmd), buf, len); wil_memcpy_toio_32(dst + sizeof(cmd), buf, len);
/* mark entry as full */ /* mark entry as full */
iowrite32(1, wil->csr + HOSTADDR(r->head) + wil_w(wil, r->head + offsetof(struct wil6210_mbox_ring_desc, sync), 1);
offsetof(struct wil6210_mbox_ring_desc, sync));
/* advance next ptr */ /* advance next ptr */
iowrite32(r->head = next_head, wil->csr + HOST_MBOX + wil_w(wil, RGF_MBOX + offsetof(struct wil6210_mbox_ctl, tx.head),
offsetof(struct wil6210_mbox_ctl, tx.head)); r->head = next_head);
trace_wil6210_wmi_cmd(&cmd.wmi, buf, len); trace_wil6210_wmi_cmd(&cmd.wmi, buf, len);
/* interrupt to FW */ /* interrupt to FW */
iowrite32(SW_INT_MBOX, wil->csr + HOST_SW_INT); wil_w(wil, RGF_USER_USER_ICR + offsetof(struct RGF_ICR, ICS),
SW_INT_MBOX);
return 0; return 0;
} }
...@@ -729,8 +729,8 @@ void wmi_recv_cmd(struct wil6210_priv *wil) ...@@ -729,8 +729,8 @@ void wmi_recv_cmd(struct wil6210_priv *wil)
u16 len; u16 len;
bool q; bool q;
r->head = ioread32(wil->csr + HOST_MBOX + r->head = wil_r(wil, RGF_MBOX +
offsetof(struct wil6210_mbox_ctl, rx.head)); offsetof(struct wil6210_mbox_ctl, rx.head));
if (r->tail == r->head) if (r->tail == r->head)
break; break;
...@@ -768,8 +768,8 @@ void wmi_recv_cmd(struct wil6210_priv *wil) ...@@ -768,8 +768,8 @@ void wmi_recv_cmd(struct wil6210_priv *wil)
cmd = (void *)&evt->event.wmi; cmd = (void *)&evt->event.wmi;
wil_memcpy_fromio_32(cmd, src, len); wil_memcpy_fromio_32(cmd, src, len);
/* mark entry as empty */ /* mark entry as empty */
iowrite32(0, wil->csr + HOSTADDR(r->tail) + wil_w(wil, r->tail +
offsetof(struct wil6210_mbox_ring_desc, sync)); offsetof(struct wil6210_mbox_ring_desc, sync), 0);
/* indicate */ /* indicate */
if ((hdr.type == WIL_MBOX_HDR_TYPE_WMI) && if ((hdr.type == WIL_MBOX_HDR_TYPE_WMI) &&
(len >= sizeof(struct wil6210_mbox_hdr_wmi))) { (len >= sizeof(struct wil6210_mbox_hdr_wmi))) {
...@@ -788,8 +788,8 @@ void wmi_recv_cmd(struct wil6210_priv *wil) ...@@ -788,8 +788,8 @@ void wmi_recv_cmd(struct wil6210_priv *wil)
/* advance tail */ /* advance tail */
r->tail = r->base + ((r->tail - r->base + r->tail = r->base + ((r->tail - r->base +
sizeof(struct wil6210_mbox_ring_desc)) % r->size); sizeof(struct wil6210_mbox_ring_desc)) % r->size);
iowrite32(r->tail, wil->csr + HOST_MBOX + wil_w(wil, RGF_MBOX +
offsetof(struct wil6210_mbox_ctl, rx.tail)); offsetof(struct wil6210_mbox_ctl, rx.tail), r->tail);
/* add to the pending list */ /* add to the pending list */
spin_lock_irqsave(&wil->wmi_ev_lock, flags); spin_lock_irqsave(&wil->wmi_ev_lock, flags);
......
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