Commit ba42156d authored by Mika Westerberg's avatar Mika Westerberg Committed by Sasha Levin

pinctrl: cherryview: Serialize all register access

[ Upstream commit 4585b000 ]

There is a hardware issue in Intel Braswell/Cherryview where concurrent
GPIO register access might results reads of 0xffffffff and writes might get
dropped.

Prevent this from happening by taking the serializing lock for all places
where it is possible that more than one thread might be accessing the
hardware concurrently.
Signed-off-by: default avatarMika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: default avatarSasha Levin <alexander.levin@verizon.com>
parent e0577738
...@@ -1169,9 +1169,12 @@ static int chv_gpio_get(struct gpio_chip *chip, unsigned offset) ...@@ -1169,9 +1169,12 @@ static int chv_gpio_get(struct gpio_chip *chip, unsigned offset)
{ {
struct chv_pinctrl *pctrl = gpiochip_to_pinctrl(chip); struct chv_pinctrl *pctrl = gpiochip_to_pinctrl(chip);
int pin = chv_gpio_offset_to_pin(pctrl, offset); int pin = chv_gpio_offset_to_pin(pctrl, offset);
unsigned long flags;
u32 ctrl0, cfg; u32 ctrl0, cfg;
spin_lock_irqsave(&pctrl->lock, flags);
ctrl0 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); ctrl0 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
spin_unlock_irqrestore(&pctrl->lock, flags);
cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK; cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;
cfg >>= CHV_PADCTRL0_GPIOCFG_SHIFT; cfg >>= CHV_PADCTRL0_GPIOCFG_SHIFT;
...@@ -1209,8 +1212,11 @@ static int chv_gpio_get_direction(struct gpio_chip *chip, unsigned offset) ...@@ -1209,8 +1212,11 @@ static int chv_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
struct chv_pinctrl *pctrl = gpiochip_to_pinctrl(chip); struct chv_pinctrl *pctrl = gpiochip_to_pinctrl(chip);
unsigned pin = chv_gpio_offset_to_pin(pctrl, offset); unsigned pin = chv_gpio_offset_to_pin(pctrl, offset);
u32 ctrl0, direction; u32 ctrl0, direction;
unsigned long flags;
spin_lock_irqsave(&pctrl->lock, flags);
ctrl0 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); ctrl0 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
spin_unlock_irqrestore(&pctrl->lock, flags);
direction = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK; direction = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;
direction >>= CHV_PADCTRL0_GPIOCFG_SHIFT; direction >>= CHV_PADCTRL0_GPIOCFG_SHIFT;
...@@ -1313,6 +1319,7 @@ static unsigned chv_gpio_irq_startup(struct irq_data *d) ...@@ -1313,6 +1319,7 @@ static unsigned chv_gpio_irq_startup(struct irq_data *d)
unsigned long flags; unsigned long flags;
u32 intsel, value; u32 intsel, value;
spin_lock_irqsave(&pctrl->lock, flags);
intsel = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0)); intsel = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
intsel &= CHV_PADCTRL0_INTSEL_MASK; intsel &= CHV_PADCTRL0_INTSEL_MASK;
intsel >>= CHV_PADCTRL0_INTSEL_SHIFT; intsel >>= CHV_PADCTRL0_INTSEL_SHIFT;
...@@ -1323,7 +1330,6 @@ static unsigned chv_gpio_irq_startup(struct irq_data *d) ...@@ -1323,7 +1330,6 @@ static unsigned chv_gpio_irq_startup(struct irq_data *d)
else else
handler = handle_edge_irq; handler = handle_edge_irq;
spin_lock_irqsave(&pctrl->lock, flags);
if (!pctrl->intr_lines[intsel]) { if (!pctrl->intr_lines[intsel]) {
__irq_set_handler_locked(d->irq, handler); __irq_set_handler_locked(d->irq, handler);
pctrl->intr_lines[intsel] = offset; pctrl->intr_lines[intsel] = offset;
......
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