Commit baba6e57 authored by Daniele Ceraolo Spurio's avatar Daniele Ceraolo Spurio Committed by Chris Wilson

drm/i915: take a reference to uncore in the engine and use it

A few advantages:

- Prepares us for the planned split of display uncore from GT uncore

- Improves our engine-centric view of the world in the engine code
  and allows us to avoid jumping back to dev_priv.

- Allows us to wrap accesses to engine register in nice macros that
  automatically pick the right mmio base.
Signed-off-by: default avatarDaniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20190325214940.23632-10-daniele.ceraolospurio@intel.com
parent 97a04e0d
...@@ -1848,7 +1848,7 @@ static int init_generic_mmio_info(struct intel_gvt *gvt) ...@@ -1848,7 +1848,7 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
MMIO_DH(GEN7_SC_INSTDONE, D_BDW_PLUS, mmio_read_from_hw, NULL); MMIO_DH(GEN7_SC_INSTDONE, D_BDW_PLUS, mmio_read_from_hw, NULL);
MMIO_GM_RDR(_MMIO(0x2148), D_ALL, NULL, NULL); MMIO_GM_RDR(_MMIO(0x2148), D_ALL, NULL, NULL);
MMIO_GM_RDR(CCID, D_ALL, NULL, NULL); MMIO_GM_RDR(CCID(RENDER_RING_BASE), D_ALL, NULL, NULL);
MMIO_GM_RDR(_MMIO(0x12198), D_ALL, NULL, NULL); MMIO_GM_RDR(_MMIO(0x12198), D_ALL, NULL, NULL);
MMIO_D(GEN7_CXT_SIZE, D_ALL); MMIO_D(GEN7_CXT_SIZE, D_ALL);
......
...@@ -880,7 +880,7 @@ static int i915_interrupt_info(struct seq_file *m, void *data) ...@@ -880,7 +880,7 @@ static int i915_interrupt_info(struct seq_file *m, void *data)
for_each_engine(engine, dev_priv, id) { for_each_engine(engine, dev_priv, id) {
seq_printf(m, seq_printf(m,
"Graphics Interrupt mask (%s): %08x\n", "Graphics Interrupt mask (%s): %08x\n",
engine->name, I915_READ_IMR(engine)); engine->name, ENGINE_READ(engine, RING_IMR));
} }
} }
......
...@@ -1136,7 +1136,7 @@ static void error_record_engine_registers(struct i915_gpu_state *error, ...@@ -1136,7 +1136,7 @@ static void error_record_engine_registers(struct i915_gpu_state *error,
struct drm_i915_private *dev_priv = engine->i915; struct drm_i915_private *dev_priv = engine->i915;
if (INTEL_GEN(dev_priv) >= 6) { if (INTEL_GEN(dev_priv) >= 6) {
ee->rc_psmi = I915_READ(RING_PSMI_CTL(engine->mmio_base)); ee->rc_psmi = ENGINE_READ(engine, RING_PSMI_CTL);
if (INTEL_GEN(dev_priv) >= 8) if (INTEL_GEN(dev_priv) >= 8)
ee->fault_reg = I915_READ(GEN8_RING_FAULT_REG); ee->fault_reg = I915_READ(GEN8_RING_FAULT_REG);
else else
...@@ -1144,32 +1144,32 @@ static void error_record_engine_registers(struct i915_gpu_state *error, ...@@ -1144,32 +1144,32 @@ static void error_record_engine_registers(struct i915_gpu_state *error,
} }
if (INTEL_GEN(dev_priv) >= 4) { if (INTEL_GEN(dev_priv) >= 4) {
ee->faddr = I915_READ(RING_DMA_FADD(engine->mmio_base)); ee->faddr = ENGINE_READ(engine, RING_DMA_FADD);
ee->ipeir = I915_READ(RING_IPEIR(engine->mmio_base)); ee->ipeir = ENGINE_READ(engine, RING_IPEIR);
ee->ipehr = I915_READ(RING_IPEHR(engine->mmio_base)); ee->ipehr = ENGINE_READ(engine, RING_IPEHR);
ee->instps = I915_READ(RING_INSTPS(engine->mmio_base)); ee->instps = ENGINE_READ(engine, RING_INSTPS);
ee->bbaddr = I915_READ(RING_BBADDR(engine->mmio_base)); ee->bbaddr = ENGINE_READ(engine, RING_BBADDR);
if (INTEL_GEN(dev_priv) >= 8) { if (INTEL_GEN(dev_priv) >= 8) {
ee->faddr |= (u64) I915_READ(RING_DMA_FADD_UDW(engine->mmio_base)) << 32; ee->faddr |= (u64)ENGINE_READ(engine, RING_DMA_FADD_UDW) << 32;
ee->bbaddr |= (u64) I915_READ(RING_BBADDR_UDW(engine->mmio_base)) << 32; ee->bbaddr |= (u64)ENGINE_READ(engine, RING_BBADDR_UDW) << 32;
} }
ee->bbstate = I915_READ(RING_BBSTATE(engine->mmio_base)); ee->bbstate = ENGINE_READ(engine, RING_BBSTATE);
} else { } else {
ee->faddr = I915_READ(DMA_FADD_I8XX); ee->faddr = ENGINE_READ(engine, DMA_FADD_I8XX);
ee->ipeir = I915_READ(IPEIR); ee->ipeir = ENGINE_READ(engine, IPEIR);
ee->ipehr = I915_READ(IPEHR); ee->ipehr = ENGINE_READ(engine, IPEHR);
} }
intel_engine_get_instdone(engine, &ee->instdone); intel_engine_get_instdone(engine, &ee->instdone);
ee->instpm = I915_READ(RING_INSTPM(engine->mmio_base)); ee->instpm = ENGINE_READ(engine, RING_INSTPM);
ee->acthd = intel_engine_get_active_head(engine); ee->acthd = intel_engine_get_active_head(engine);
ee->start = I915_READ_START(engine); ee->start = ENGINE_READ(engine, RING_START);
ee->head = I915_READ_HEAD(engine); ee->head = ENGINE_READ(engine, RING_HEAD);
ee->tail = I915_READ_TAIL(engine); ee->tail = ENGINE_READ(engine, RING_TAIL);
ee->ctl = I915_READ_CTL(engine); ee->ctl = ENGINE_READ(engine, RING_CTL);
if (INTEL_GEN(dev_priv) > 2) if (INTEL_GEN(dev_priv) > 2)
ee->mode = I915_READ_MODE(engine); ee->mode = ENGINE_READ(engine, RING_MI_MODE);
if (!HWS_NEEDS_PHYSICAL(dev_priv)) { if (!HWS_NEEDS_PHYSICAL(dev_priv)) {
i915_reg_t mmio; i915_reg_t mmio;
...@@ -1214,10 +1214,10 @@ static void error_record_engine_registers(struct i915_gpu_state *error, ...@@ -1214,10 +1214,10 @@ static void error_record_engine_registers(struct i915_gpu_state *error,
if (IS_GEN(dev_priv, 6)) if (IS_GEN(dev_priv, 6))
ee->vm_info.pp_dir_base = ee->vm_info.pp_dir_base =
I915_READ(RING_PP_DIR_BASE_READ(engine)); ENGINE_READ(engine, RING_PP_DIR_BASE_READ);
else if (IS_GEN(dev_priv, 7)) else if (IS_GEN(dev_priv, 7))
ee->vm_info.pp_dir_base = ee->vm_info.pp_dir_base =
I915_READ(RING_PP_DIR_BASE(engine)); ENGINE_READ(engine, RING_PP_DIR_BASE);
else if (INTEL_GEN(dev_priv) >= 8) else if (INTEL_GEN(dev_priv) >= 8)
for (i = 0; i < 4; i++) { for (i = 0; i < 4; i++) {
ee->vm_info.pdp[i] = ee->vm_info.pdp[i] =
...@@ -1601,7 +1601,7 @@ static void capture_reg_state(struct i915_gpu_state *error) ...@@ -1601,7 +1601,7 @@ static void capture_reg_state(struct i915_gpu_state *error)
} }
if (INTEL_GEN(dev_priv) >= 5) if (INTEL_GEN(dev_priv) >= 5)
error->ccid = I915_READ(CCID); error->ccid = I915_READ(CCID(RENDER_RING_BASE));
/* 3: Feature specific registers */ /* 3: Feature specific registers */
if (IS_GEN_RANGE(dev_priv, 6, 7)) { if (IS_GEN_RANGE(dev_priv, 6, 7)) {
......
...@@ -434,9 +434,9 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) ...@@ -434,9 +434,9 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define GEN11_VECS_SFC_USAGE(engine) _MMIO((engine)->mmio_base + 0x2014) #define GEN11_VECS_SFC_USAGE(engine) _MMIO((engine)->mmio_base + 0x2014)
#define GEN11_VECS_SFC_USAGE_BIT (1 << 0) #define GEN11_VECS_SFC_USAGE_BIT (1 << 0)
#define RING_PP_DIR_BASE(engine) _MMIO((engine)->mmio_base + 0x228) #define RING_PP_DIR_BASE(base) _MMIO((base) + 0x228)
#define RING_PP_DIR_BASE_READ(engine) _MMIO((engine)->mmio_base + 0x518) #define RING_PP_DIR_BASE_READ(base) _MMIO((base) + 0x518)
#define RING_PP_DIR_DCLV(engine) _MMIO((engine)->mmio_base + 0x220) #define RING_PP_DIR_DCLV(base) _MMIO((base) + 0x220)
#define PP_DIR_DCLV_2G 0xffffffff #define PP_DIR_DCLV_2G 0xffffffff
#define GEN8_RING_PDP_UDW(engine, n) _MMIO((engine)->mmio_base + 0x270 + (n) * 8 + 4) #define GEN8_RING_PDP_UDW(engine, n) _MMIO((engine)->mmio_base + 0x270 + (n) * 8 + 4)
...@@ -2568,12 +2568,12 @@ enum i915_power_well_id { ...@@ -2568,12 +2568,12 @@ enum i915_power_well_id {
#define HWS_START_ADDRESS_SHIFT 4 #define HWS_START_ADDRESS_SHIFT 4
#define PWRCTXA _MMIO(0x2088) /* 965GM+ only */ #define PWRCTXA _MMIO(0x2088) /* 965GM+ only */
#define PWRCTX_EN (1 << 0) #define PWRCTX_EN (1 << 0)
#define IPEIR _MMIO(0x2088) #define IPEIR(base) _MMIO((base) + 0x88)
#define IPEHR _MMIO(0x208c) #define IPEHR(base) _MMIO((base) + 0x8c)
#define GEN2_INSTDONE _MMIO(0x2090) #define GEN2_INSTDONE _MMIO(0x2090)
#define NOPID _MMIO(0x2094) #define NOPID _MMIO(0x2094)
#define HWSTAM _MMIO(0x2098) #define HWSTAM _MMIO(0x2098)
#define DMA_FADD_I8XX _MMIO(0x20d0) #define DMA_FADD_I8XX(base) _MMIO((base) + 0xd0)
#define RING_BBSTATE(base) _MMIO((base) + 0x110) #define RING_BBSTATE(base) _MMIO((base) + 0x110)
#define RING_BB_PPGTT (1 << 5) #define RING_BB_PPGTT (1 << 5)
#define RING_SBBADDR(base) _MMIO((base) + 0x114) /* hsw+ */ #define RING_SBBADDR(base) _MMIO((base) + 0x114) /* hsw+ */
...@@ -2747,7 +2747,7 @@ enum i915_power_well_id { ...@@ -2747,7 +2747,7 @@ enum i915_power_well_id {
#define INSTPM_FORCE_ORDERING (1 << 7) /* GEN6+ */ #define INSTPM_FORCE_ORDERING (1 << 7) /* GEN6+ */
#define INSTPM_TLB_INVALIDATE (1 << 9) #define INSTPM_TLB_INVALIDATE (1 << 9)
#define INSTPM_SYNC_FLUSH (1 << 5) #define INSTPM_SYNC_FLUSH (1 << 5)
#define ACTHD _MMIO(0x20c8) #define ACTHD(base) _MMIO((base) + 0xc8)
#define MEM_MODE _MMIO(0x20cc) #define MEM_MODE _MMIO(0x20cc)
#define MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1 << 3) /* 830 only */ #define MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1 << 3) /* 830 only */
#define MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1 << 2) /* 830/845 only */ #define MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1 << 2) /* 830/845 only */
...@@ -3947,7 +3947,7 @@ enum i915_power_well_id { ...@@ -3947,7 +3947,7 @@ enum i915_power_well_id {
/* /*
* Logical Context regs * Logical Context regs
*/ */
#define CCID _MMIO(0x2180) #define CCID(base) _MMIO((base) + 0x180)
#define CCID_EN BIT(0) #define CCID_EN BIT(0)
#define CCID_EXTENDED_STATE_RESTORE BIT(2) #define CCID_EXTENDED_STATE_RESTORE BIT(2)
#define CCID_EXTENDED_STATE_SAVE BIT(3) #define CCID_EXTENDED_STATE_SAVE BIT(3)
......
...@@ -1173,19 +1173,24 @@ static void i915_reset_device(struct drm_i915_private *i915, ...@@ -1173,19 +1173,24 @@ static void i915_reset_device(struct drm_i915_private *i915,
kobject_uevent_env(kobj, KOBJ_CHANGE, reset_done_event); kobject_uevent_env(kobj, KOBJ_CHANGE, reset_done_event);
} }
static void clear_register(struct drm_i915_private *dev_priv, i915_reg_t reg)
{
I915_WRITE(reg, I915_READ(reg));
}
void i915_clear_error_registers(struct drm_i915_private *dev_priv) void i915_clear_error_registers(struct drm_i915_private *dev_priv)
{ {
u32 eir; u32 eir;
if (!IS_GEN(dev_priv, 2)) if (!IS_GEN(dev_priv, 2))
I915_WRITE(PGTBL_ER, I915_READ(PGTBL_ER)); clear_register(dev_priv, PGTBL_ER);
if (INTEL_GEN(dev_priv) < 4) if (INTEL_GEN(dev_priv) < 4)
I915_WRITE(IPEIR, I915_READ(IPEIR)); clear_register(dev_priv, IPEIR(RENDER_RING_BASE));
else else
I915_WRITE(IPEIR_I965, I915_READ(IPEIR_I965)); clear_register(dev_priv, IPEIR_I965);
I915_WRITE(EIR, I915_READ(EIR)); clear_register(dev_priv, EIR);
eir = I915_READ(EIR); eir = I915_READ(EIR);
if (eir) { if (eir) {
/* /*
......
This diff is collapsed.
...@@ -29,6 +29,7 @@ struct drm_i915_reg_table; ...@@ -29,6 +29,7 @@ struct drm_i915_reg_table;
struct i915_gem_context; struct i915_gem_context;
struct i915_request; struct i915_request;
struct i915_sched_attr; struct i915_sched_attr;
struct intel_uncore;
struct intel_hw_status_page { struct intel_hw_status_page {
struct i915_vma *vma; struct i915_vma *vma;
...@@ -250,6 +251,7 @@ struct intel_engine_execlists { ...@@ -250,6 +251,7 @@ struct intel_engine_execlists {
struct intel_engine_cs { struct intel_engine_cs {
struct drm_i915_private *i915; struct drm_i915_private *i915;
struct intel_uncore *uncore;
char name[INTEL_ENGINE_CS_MAX_NAME]; char name[INTEL_ENGINE_CS_MAX_NAME];
enum intel_engine_id id; enum intel_engine_id id;
......
...@@ -118,11 +118,11 @@ engine_stuck(struct intel_engine_cs *engine, u64 acthd) ...@@ -118,11 +118,11 @@ engine_stuck(struct intel_engine_cs *engine, u64 acthd)
* and break the hang. This should work on * and break the hang. This should work on
* all but the second generation chipsets. * all but the second generation chipsets.
*/ */
tmp = I915_READ_CTL(engine); tmp = ENGINE_READ(engine, RING_CTL);
if (tmp & RING_WAIT) { if (tmp & RING_WAIT) {
i915_handle_error(dev_priv, engine->mask, 0, i915_handle_error(dev_priv, engine->mask, 0,
"stuck wait on %s", engine->name); "stuck wait on %s", engine->name);
I915_WRITE_CTL(engine, tmp); ENGINE_WRITE(engine, RING_CTL, tmp);
return ENGINE_WAIT_KICK; return ENGINE_WAIT_KICK;
} }
......
...@@ -2074,16 +2074,14 @@ static int gen8_emit_bb_start(struct i915_request *rq, ...@@ -2074,16 +2074,14 @@ static int gen8_emit_bb_start(struct i915_request *rq,
static void gen8_logical_ring_enable_irq(struct intel_engine_cs *engine) static void gen8_logical_ring_enable_irq(struct intel_engine_cs *engine)
{ {
struct drm_i915_private *dev_priv = engine->i915; ENGINE_WRITE(engine, RING_IMR,
I915_WRITE_IMR(engine, ~(engine->irq_enable_mask | engine->irq_keep_mask));
~(engine->irq_enable_mask | engine->irq_keep_mask)); ENGINE_POSTING_READ(engine, RING_IMR);
POSTING_READ_FW(RING_IMR(engine->mmio_base));
} }
static void gen8_logical_ring_disable_irq(struct intel_engine_cs *engine) static void gen8_logical_ring_disable_irq(struct intel_engine_cs *engine)
{ {
struct drm_i915_private *dev_priv = engine->i915; ENGINE_WRITE(engine, RING_IMR, ~engine->irq_keep_mask);
I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
} }
static int gen8_emit_flush(struct i915_request *request, u32 mode) static int gen8_emit_flush(struct i915_request *request, u32 mode)
...@@ -2288,7 +2286,7 @@ void intel_logical_ring_cleanup(struct intel_engine_cs *engine) ...@@ -2288,7 +2286,7 @@ void intel_logical_ring_cleanup(struct intel_engine_cs *engine)
dev_priv = engine->i915; dev_priv = engine->i915;
if (engine->buffer) { if (engine->buffer) {
WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0); WARN_ON((ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE) == 0);
} }
if (engine->cleanup) if (engine->cleanup)
...@@ -2400,6 +2398,7 @@ static int logical_ring_init(struct intel_engine_cs *engine) ...@@ -2400,6 +2398,7 @@ static int logical_ring_init(struct intel_engine_cs *engine)
{ {
struct drm_i915_private *i915 = engine->i915; struct drm_i915_private *i915 = engine->i915;
struct intel_engine_execlists * const execlists = &engine->execlists; struct intel_engine_execlists * const execlists = &engine->execlists;
u32 base = engine->mmio_base;
int ret; int ret;
ret = intel_engine_init_common(engine); ret = intel_engine_init_common(engine);
...@@ -2410,12 +2409,12 @@ static int logical_ring_init(struct intel_engine_cs *engine) ...@@ -2410,12 +2409,12 @@ static int logical_ring_init(struct intel_engine_cs *engine)
if (HAS_LOGICAL_RING_ELSQ(i915)) { if (HAS_LOGICAL_RING_ELSQ(i915)) {
execlists->submit_reg = i915->uncore.regs + execlists->submit_reg = i915->uncore.regs +
i915_mmio_reg_offset(RING_EXECLIST_SQ_CONTENTS(engine)); i915_mmio_reg_offset(RING_EXECLIST_SQ_CONTENTS(base));
execlists->ctrl_reg = i915->uncore.regs + execlists->ctrl_reg = i915->uncore.regs +
i915_mmio_reg_offset(RING_EXECLIST_CONTROL(engine)); i915_mmio_reg_offset(RING_EXECLIST_CONTROL(base));
} else { } else {
execlists->submit_reg = i915->uncore.regs + execlists->submit_reg = i915->uncore.regs +
i915_mmio_reg_offset(RING_ELSP(engine)); i915_mmio_reg_offset(RING_ELSP(base));
} }
execlists->preempt_complete_status = ~0u; execlists->preempt_complete_status = ~0u;
...@@ -2658,7 +2657,7 @@ static void execlists_init_reg_state(u32 *regs, ...@@ -2658,7 +2657,7 @@ static void execlists_init_reg_state(u32 *regs,
regs[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(rcs ? 14 : 11) | regs[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(rcs ? 14 : 11) |
MI_LRI_FORCE_POSTED; MI_LRI_FORCE_POSTED;
CTX_REG(regs, CTX_CONTEXT_CONTROL, RING_CONTEXT_CONTROL(engine), CTX_REG(regs, CTX_CONTEXT_CONTROL, RING_CONTEXT_CONTROL(base),
_MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT) | _MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT) |
_MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH)); _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH));
if (INTEL_GEN(engine->i915) < 11) { if (INTEL_GEN(engine->i915) < 11) {
......
...@@ -28,20 +28,20 @@ ...@@ -28,20 +28,20 @@
#include "i915_gem_context.h" #include "i915_gem_context.h"
/* Execlists regs */ /* Execlists regs */
#define RING_ELSP(engine) _MMIO((engine)->mmio_base + 0x230) #define RING_ELSP(base) _MMIO((base) + 0x230)
#define RING_EXECLIST_STATUS_LO(engine) _MMIO((engine)->mmio_base + 0x234) #define RING_EXECLIST_STATUS_LO(base) _MMIO((base) + 0x234)
#define RING_EXECLIST_STATUS_HI(engine) _MMIO((engine)->mmio_base + 0x234 + 4) #define RING_EXECLIST_STATUS_HI(base) _MMIO((base) + 0x234 + 4)
#define RING_CONTEXT_CONTROL(engine) _MMIO((engine)->mmio_base + 0x244) #define RING_CONTEXT_CONTROL(base) _MMIO((base) + 0x244)
#define CTX_CTRL_INHIBIT_SYN_CTX_SWITCH (1 << 3) #define CTX_CTRL_INHIBIT_SYN_CTX_SWITCH (1 << 3)
#define CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT (1 << 0) #define CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT (1 << 0)
#define CTX_CTRL_RS_CTX_ENABLE (1 << 1) #define CTX_CTRL_RS_CTX_ENABLE (1 << 1)
#define CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT (1 << 2) #define CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT (1 << 2)
#define RING_CONTEXT_STATUS_BUF_BASE(engine) _MMIO((engine)->mmio_base + 0x370) #define RING_CONTEXT_STATUS_BUF_BASE(base) _MMIO((base) + 0x370)
#define RING_CONTEXT_STATUS_BUF_LO(engine, i) _MMIO((engine)->mmio_base + 0x370 + (i) * 8) #define RING_CONTEXT_STATUS_BUF_LO(base, i) _MMIO((base) + 0x370 + (i) * 8)
#define RING_CONTEXT_STATUS_BUF_HI(engine, i) _MMIO((engine)->mmio_base + 0x370 + (i) * 8 + 4) #define RING_CONTEXT_STATUS_BUF_HI(base, i) _MMIO((base) + 0x370 + (i) * 8 + 4)
#define RING_CONTEXT_STATUS_PTR(engine) _MMIO((engine)->mmio_base + 0x3a0) #define RING_CONTEXT_STATUS_PTR(base) _MMIO((base) + 0x3a0)
#define RING_EXECLIST_SQ_CONTENTS(engine) _MMIO((engine)->mmio_base + 0x510) #define RING_EXECLIST_SQ_CONTENTS(base) _MMIO((base) + 0x510)
#define RING_EXECLIST_CONTROL(engine) _MMIO((engine)->mmio_base + 0x550) #define RING_EXECLIST_CONTROL(base) _MMIO((base) + 0x550)
#define EL_CTRL_LOAD (1 << 0) #define EL_CTRL_LOAD (1 << 0)
/* The docs specify that the write pointer wraps around after 5h, "After status /* The docs specify that the write pointer wraps around after 5h, "After status
......
This diff is collapsed.
...@@ -29,23 +29,44 @@ struct drm_printer; ...@@ -29,23 +29,44 @@ struct drm_printer;
#define CACHELINE_BYTES 64 #define CACHELINE_BYTES 64
#define CACHELINE_DWORDS (CACHELINE_BYTES / sizeof(u32)) #define CACHELINE_DWORDS (CACHELINE_BYTES / sizeof(u32))
#define I915_READ_TAIL(engine) I915_READ(RING_TAIL((engine)->mmio_base)) /*
#define I915_WRITE_TAIL(engine, val) I915_WRITE(RING_TAIL((engine)->mmio_base), val) * The register defines to be used with the following macros need to accept a
* base param, e.g:
*
* REG_FOO(base) _MMIO((base) + <relative offset>)
* ENGINE_READ(engine, REG_FOO);
*
* register arrays are to be defined and accessed as follows:
*
* REG_BAR(base, i) _MMIO((base) + <relative offset> + (i) * <shift>)
* ENGINE_READ_IDX(engine, REG_BAR, i)
*/
#define __ENGINE_REG_OP(op__, engine__, ...) \
intel_uncore_##op__((engine__)->uncore, __VA_ARGS__)
#define __ENGINE_READ_OP(op__, engine__, reg__) \
__ENGINE_REG_OP(op__, (engine__), reg__((engine__)->mmio_base))
#define I915_READ_START(engine) I915_READ(RING_START((engine)->mmio_base)) #define ENGINE_READ16(...) __ENGINE_READ_OP(read16, __VA_ARGS__)
#define I915_WRITE_START(engine, val) I915_WRITE(RING_START((engine)->mmio_base), val) #define ENGINE_READ(...) __ENGINE_READ_OP(read, __VA_ARGS__)
#define ENGINE_READ_FW(...) __ENGINE_READ_OP(read_fw, __VA_ARGS__)
#define ENGINE_POSTING_READ(...) __ENGINE_READ_OP(posting_read, __VA_ARGS__)
#define I915_READ_HEAD(engine) I915_READ(RING_HEAD((engine)->mmio_base)) #define ENGINE_READ64(engine__, lower_reg__, upper_reg__) \
#define I915_WRITE_HEAD(engine, val) I915_WRITE(RING_HEAD((engine)->mmio_base), val) __ENGINE_REG_OP(read64_2x32, (engine__), \
lower_reg__((engine__)->mmio_base), \
upper_reg__((engine__)->mmio_base))
#define I915_READ_CTL(engine) I915_READ(RING_CTL((engine)->mmio_base)) #define ENGINE_READ_IDX(engine__, reg__, idx__) \
#define I915_WRITE_CTL(engine, val) I915_WRITE(RING_CTL((engine)->mmio_base), val) __ENGINE_REG_OP(read, (engine__), reg__((engine__)->mmio_base, (idx__)))
#define I915_READ_IMR(engine) I915_READ(RING_IMR((engine)->mmio_base)) #define __ENGINE_WRITE_OP(op__, engine__, reg__, val__) \
#define I915_WRITE_IMR(engine, val) I915_WRITE(RING_IMR((engine)->mmio_base), val) __ENGINE_REG_OP(op__, (engine__), reg__((engine__)->mmio_base), (val__))
#define I915_READ_MODE(engine) I915_READ(RING_MI_MODE((engine)->mmio_base)) #define ENGINE_WRITE16(...) __ENGINE_WRITE_OP(write16, __VA_ARGS__)
#define I915_WRITE_MODE(engine, val) I915_WRITE(RING_MI_MODE((engine)->mmio_base), val) #define ENGINE_WRITE(...) __ENGINE_WRITE_OP(write, __VA_ARGS__)
#define ENGINE_WRITE_FW(...) __ENGINE_WRITE_OP(write_fw, __VA_ARGS__)
/* seqno size is actually only a uint32, but since we plan to use MI_FLUSH_DW to /* seqno size is actually only a uint32, but since we plan to use MI_FLUSH_DW to
* do the writes, and that must have qw aligned offsets, simply pretend it's 8b. * do the writes, and that must have qw aligned offsets, simply pretend it's 8b.
......
...@@ -1814,7 +1814,7 @@ int __intel_wait_for_register_fw(struct intel_uncore *uncore, ...@@ -1814,7 +1814,7 @@ int __intel_wait_for_register_fw(struct intel_uncore *uncore,
/** /**
* __intel_wait_for_register - wait until register matches expected state * __intel_wait_for_register - wait until register matches expected state
* @dev_priv: the i915 device * @uncore: the struct intel_uncore
* @reg: the register to read * @reg: the register to read
* @mask: mask to apply to register value * @mask: mask to apply to register value
* @value: expected value * @value: expected value
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment