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Commit bb19a751 authored by Kukjin Kim's avatar Kukjin Kim
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ARM: EXYNOS: add interrupt definitions for EXYNOS5250 

This patch adds the interrupt definitions for EXYNOS5250 at
<mach/irqs.h> file and it is needed for EXYNOS5250 SoC.
As a note, for single zImage of EXYNOS4 and EXYNOS5, prefix
of EXYNOS4_ and EXYNOS5_ has been added.
Signed-off-by: default avatarKukjin Kim <kgene.kim@samsung.com>
parent 94c7ca71
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Showing with 558 additions and 208 deletions
arch/arm/mach-exynos/common.c
View file @ bb19a751
......@@ -345,6 +345,11 @@ static void __init exynos5_map_io(void)
{
iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
s3c_device_i2c0.resource[0].start = EXYNOS5_PA_IIC(0);
s3c_device_i2c0.resource[0].end = EXYNOS5_PA_IIC(0) + SZ_4K - 1;
s3c_device_i2c0.resource[1].start = EXYNOS5_IRQ_IIC;
s3c_device_i2c0.resource[1].end = EXYNOS5_IRQ_IIC;
/* The I2C bus controllers are directly compatible with s3c2440 */
s3c_i2c0_setname("s3c2440-i2c");
s3c_i2c1_setname("s3c2440-i2c");
......@@ -451,7 +456,14 @@ static struct irq_chip combiner_chip = {
static void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq)
{
if (combiner_nr >= MAX_COMBINER_NR)
unsigned int max_nr;
if (soc_is_exynos5250())
max_nr = EXYNOS5_MAX_COMBINER_NR;
else
max_nr = EXYNOS4_MAX_COMBINER_NR;
if (combiner_nr >= max_nr)
BUG();
if (irq_set_handler_data(irq, &combiner_data[combiner_nr]) != 0)
BUG();
......@@ -462,8 +474,14 @@ static void __init combiner_init(unsigned int combiner_nr, void __iomem *base,
unsigned int irq_start)
{
unsigned int i;
unsigned int max_nr;
if (combiner_nr >= MAX_COMBINER_NR)
if (soc_is_exynos5250())
max_nr = EXYNOS5_MAX_COMBINER_NR;
else
max_nr = EXYNOS4_MAX_COMBINER_NR;
if (combiner_nr >= max_nr)
BUG();
combiner_data[combiner_nr].base = base;
......@@ -506,7 +524,7 @@ void __init exynos4_init_irq(void)
of_irq_init(exynos4_dt_irq_match);
#endif
for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
for (irq = 0; irq < EXYNOS4_MAX_COMBINER_NR; irq++) {
combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
COMBINER_IRQ(irq, 0));
......@@ -527,7 +545,7 @@ void __init exynos5_init_irq(void)
gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
for (irq = 0; irq < EXYNOS5_MAX_COMBINER_NR; irq++) {
combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
COMBINER_IRQ(irq, 0));
combiner_cascade_irq(irq, IRQ_SPI(irq));
......@@ -651,27 +669,43 @@ static DEFINE_SPINLOCK(eint_lock);
static unsigned int eint0_15_data[16];
static unsigned int exynos4_get_irq_nr(unsigned int number)
{
u32 ret = 0;
switch (number) {
case 0 ... 3:
ret = (number + IRQ_EINT0);
break;
case 4 ... 7:
ret = (number + (IRQ_EINT4 - 4));
break;
case 8 ... 15:
ret = (number + (IRQ_EINT8 - 8));
break;
default:
printk(KERN_ERR "number available : %d\n", number);
}
return ret;
}
static unsigned int exynos4_eint0_15_src_int[16] = {
EXYNOS4_IRQ_EINT0,
EXYNOS4_IRQ_EINT1,
EXYNOS4_IRQ_EINT2,
EXYNOS4_IRQ_EINT3,
EXYNOS4_IRQ_EINT4,
EXYNOS4_IRQ_EINT5,
EXYNOS4_IRQ_EINT6,
EXYNOS4_IRQ_EINT7,
EXYNOS4_IRQ_EINT8,
EXYNOS4_IRQ_EINT9,
EXYNOS4_IRQ_EINT10,
EXYNOS4_IRQ_EINT11,
EXYNOS4_IRQ_EINT12,
EXYNOS4_IRQ_EINT13,
EXYNOS4_IRQ_EINT14,
EXYNOS4_IRQ_EINT15,
};
static unsigned int exynos5_eint0_15_src_int[16] = {
EXYNOS5_IRQ_EINT0,
EXYNOS5_IRQ_EINT1,
EXYNOS5_IRQ_EINT2,
EXYNOS5_IRQ_EINT3,
EXYNOS5_IRQ_EINT4,
EXYNOS5_IRQ_EINT5,
EXYNOS5_IRQ_EINT6,
EXYNOS5_IRQ_EINT7,
EXYNOS5_IRQ_EINT8,
EXYNOS5_IRQ_EINT9,
EXYNOS5_IRQ_EINT10,
EXYNOS5_IRQ_EINT11,
EXYNOS5_IRQ_EINT12,
EXYNOS5_IRQ_EINT13,
EXYNOS5_IRQ_EINT14,
EXYNOS5_IRQ_EINT15,
};
static inline void exynos4_irq_eint_mask(struct irq_data *data)
{
u32 mask;
......@@ -816,7 +850,7 @@ static void exynos4_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
chained_irq_exit(chip, desc);
}
static void exynos4_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
{
u32 *irq_data = irq_get_handler_data(irq);
struct irq_chip *chip = irq_get_chip(irq);
......@@ -846,15 +880,22 @@ static int __init exynos4_init_irq_eint(void)
set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
}
irq_set_chained_handler(IRQ_EINT16_31, exynos4_irq_demux_eint16_31);
irq_set_chained_handler(EXYNOS_IRQ_EINT16_31, exynos4_irq_demux_eint16_31);
for (irq = 0 ; irq <= 15 ; irq++) {
eint0_15_data[irq] = IRQ_EINT(irq);
irq_set_handler_data(exynos4_get_irq_nr(irq),
&eint0_15_data[irq]);
irq_set_chained_handler(exynos4_get_irq_nr(irq),
exynos4_irq_eint0_15);
if (soc_is_exynos5250()) {
irq_set_handler_data(exynos5_eint0_15_src_int[irq],
&eint0_15_data[irq]);
irq_set_chained_handler(exynos5_eint0_15_src_int[irq],
exynos_irq_eint0_15);
} else {
irq_set_handler_data(exynos4_eint0_15_src_int[irq],
&eint0_15_data[irq]);
irq_set_chained_handler(exynos4_eint0_15_src_int[irq],
exynos_irq_eint0_15);
}
}
return 0;
......
arch/arm/mach-exynos/dev-ahci.c
View file @ bb19a751
......@@ -242,8 +242,8 @@ static struct resource exynos4_ahci_resource[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_SATA,
.end = IRQ_SATA,
.start = EXYNOS4_IRQ_SATA,
.end = EXYNOS4_IRQ_SATA,
.flags = IORESOURCE_IRQ,
},
};
......
arch/arm/mach-exynos/dev-audio.c
View file @ bb19a751
......@@ -304,8 +304,8 @@ static struct resource exynos4_ac97_resource[] = {
.flags = IORESOURCE_DMA,
},
[4] = {
.start = IRQ_AC97,
.end = IRQ_AC97,
.start = EXYNOS4_IRQ_AC97,
.end = EXYNOS4_IRQ_AC97,
.flags = IORESOURCE_IRQ,
},
};
......
arch/arm/mach-exynos/dma.c
View file @ bb19a751
......@@ -108,7 +108,7 @@ static u8 exynos4212_pdma0_peri[] = {
struct dma_pl330_platdata exynos4_pdma0_pdata;
static AMBA_AHB_DEVICE(exynos4_pdma0, "dma-pl330.0", 0x00041330,
EXYNOS4_PA_PDMA0, {IRQ_PDMA0}, &exynos4_pdma0_pdata);
EXYNOS4_PA_PDMA0, {EXYNOS4_IRQ_PDMA0}, &exynos4_pdma0_pdata);
static u8 exynos4210_pdma1_peri[] = {
DMACH_PCM0_RX,
......@@ -174,7 +174,7 @@ static u8 exynos4212_pdma1_peri[] = {
static struct dma_pl330_platdata exynos4_pdma1_pdata;
static AMBA_AHB_DEVICE(exynos4_pdma1, "dma-pl330.1", 0x00041330,
EXYNOS4_PA_PDMA1, {IRQ_PDMA1}, &exynos4_pdma1_pdata);
EXYNOS4_PA_PDMA1, {EXYNOS4_IRQ_PDMA1}, &exynos4_pdma1_pdata);
static u8 mdma_peri[] = {
DMACH_MTOM_0,
......@@ -193,7 +193,7 @@ static struct dma_pl330_platdata exynos4_mdma1_pdata = {
};
static AMBA_AHB_DEVICE(exynos4_mdma1, "dma-pl330.2", 0x00041330,
EXYNOS4_PA_MDMA1, {IRQ_MDMA1}, &exynos4_mdma1_pdata);
EXYNOS4_PA_MDMA1, {EXYNOS4_IRQ_MDMA1}, &exynos4_mdma1_pdata);
static int __init exynos4_dma_init(void)
{
......
arch/arm/mach-exynos/include/mach/irqs.h
View file @ bb19a751
This diff is collapsed.
arch/arm/mach-exynos/mct.c
View file @ bb19a751
......@@ -258,7 +258,10 @@ static void exynos4_clockevent_init(void)
mct_comp_device.cpumask = cpumask_of(0);
clockevents_register_device(&mct_comp_device);
setup_irq(IRQ_MCT_G0, &mct_comp_event_irq);
if (soc_is_exynos5250())
setup_irq(EXYNOS5_IRQ_MCT_G0, &mct_comp_event_irq);
else
setup_irq(EXYNOS4_IRQ_MCT_G0, &mct_comp_event_irq);
}
#ifdef CONFIG_LOCAL_TIMERS
......@@ -406,16 +409,16 @@ static void exynos4_mct_tick_init(struct clock_event_device *evt)
if (mct_int_type == MCT_INT_SPI) {
if (cpu == 0) {
mct_tick0_event_irq.dev_id = mevt;
evt->irq = IRQ_MCT_L0;
setup_irq(IRQ_MCT_L0, &mct_tick0_event_irq);
evt->irq = EXYNOS4_IRQ_MCT_L0;
setup_irq(EXYNOS4_IRQ_MCT_L0, &mct_tick0_event_irq);
} else {
mct_tick1_event_irq.dev_id = mevt;
evt->irq = IRQ_MCT_L1;
setup_irq(IRQ_MCT_L1, &mct_tick1_event_irq);
irq_set_affinity(IRQ_MCT_L1, cpumask_of(1));
evt->irq = EXYNOS4_IRQ_MCT_L1;
setup_irq(EXYNOS4_IRQ_MCT_L1, &mct_tick1_event_irq);
irq_set_affinity(EXYNOS4_IRQ_MCT_L1, cpumask_of(1));
}
} else {
enable_percpu_irq(IRQ_MCT_LOCALTIMER, 0);
enable_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER, 0);
}
}
......@@ -437,7 +440,7 @@ void local_timer_stop(struct clock_event_device *evt)
else
remove_irq(evt->irq, &mct_tick1_event_irq);
else
disable_percpu_irq(IRQ_MCT_LOCALTIMER);
disable_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER);
}
#endif /* CONFIG_LOCAL_TIMERS */
......@@ -452,11 +455,11 @@ static void __init exynos4_timer_resources(void)
if (mct_int_type == MCT_INT_PPI) {
int err;
err = request_percpu_irq(IRQ_MCT_LOCALTIMER,
err = request_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER,
exynos4_mct_tick_isr, "MCT",
&percpu_mct_tick);
WARN(err, "MCT: can't request IRQ %d (%d)\n",
IRQ_MCT_LOCALTIMER, err);
EXYNOS_IRQ_MCT_LOCALTIMER, err);
}
#endif /* CONFIG_LOCAL_TIMERS */
}
......
arch/arm/plat-s5p/irq-pm.c
View file @ bb19a751
......@@ -39,19 +39,32 @@ unsigned long s3c_irqwake_eintallow = 0xffffffffL;
int s3c_irq_wake(struct irq_data *data, unsigned int state)
{
unsigned long irqbit;
unsigned int irq_rtc_tic, irq_rtc_alarm;
#ifdef CONFIG_ARCH_EXYNOS
if (soc_is_exynos5250()) {
irq_rtc_tic = EXYNOS5_IRQ_RTC_TIC;
irq_rtc_alarm = EXYNOS5_IRQ_RTC_ALARM;
} else {
irq_rtc_tic = EXYNOS4_IRQ_RTC_TIC;
irq_rtc_alarm = EXYNOS4_IRQ_RTC_ALARM;
}
#else
irq_rtc_tic = IRQ_RTC_TIC;
irq_rtc_alarm = IRQ_RTC_ALARM;
#endif
if (data->irq == irq_rtc_tic || data->irq == irq_rtc_alarm) {
irqbit = 1 << (data->irq + 1 - irq_rtc_alarm);
switch (data->irq) {
case IRQ_RTC_TIC:
case IRQ_RTC_ALARM:
irqbit = 1 << (data->irq + 1 - IRQ_RTC_ALARM);
if (!state)
s3c_irqwake_intmask |= irqbit;
else
s3c_irqwake_intmask &= ~irqbit;
break;
default:
} else {
return -ENOENT;
}
return 0;
}
......
arch/arm/plat-samsung/irq-vic-timer.c
View file @ bb19a751
......@@ -19,6 +19,7 @@
#include <linux/io.h>
#include <mach/map.h>
#include <plat/cpu.h>
#include <plat/irq-vic-timer.h>
#include <plat/regs-timer.h>
......@@ -57,6 +58,21 @@ void __init s3c_init_vic_timer_irq(unsigned int num, unsigned int timer_irq)
struct irq_chip_type *ct;
unsigned int i;
#ifdef CONFIG_ARCH_EXYNOS
if (soc_is_exynos5250()) {
pirq[0] = EXYNOS5_IRQ_TIMER0_VIC;
pirq[1] = EXYNOS5_IRQ_TIMER1_VIC;
pirq[2] = EXYNOS5_IRQ_TIMER2_VIC;
pirq[3] = EXYNOS5_IRQ_TIMER3_VIC;
pirq[4] = EXYNOS5_IRQ_TIMER4_VIC;
} else {
pirq[0] = EXYNOS4_IRQ_TIMER0_VIC;
pirq[1] = EXYNOS4_IRQ_TIMER1_VIC;
pirq[2] = EXYNOS4_IRQ_TIMER2_VIC;
pirq[3] = EXYNOS4_IRQ_TIMER3_VIC;
pirq[4] = EXYNOS4_IRQ_TIMER4_VIC;
}
#endif
s3c_tgc = irq_alloc_generic_chip("s3c-timer", 1, timer_irq,
S3C64XX_TINT_CSTAT, handle_level_irq);
......
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