Commit bb2ac47b authored by Alexander Duyck's avatar Alexander Duyck Committed by David S. Miller

igb: add support for 82580 MAC

This patch adds support for the 82580 MAC.
Signed-off-by: default avatarAlexander Duyck <alexander.h.duyck@intel.com>
Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 2909c3f7
This diff is collapsed.
...@@ -38,6 +38,11 @@ extern void igb_rx_fifo_flush_82575(struct e1000_hw *hw); ...@@ -38,6 +38,11 @@ extern void igb_rx_fifo_flush_82575(struct e1000_hw *hw);
#define E1000_RAR_ENTRIES_82575 16 #define E1000_RAR_ENTRIES_82575 16
#define E1000_RAR_ENTRIES_82576 24 #define E1000_RAR_ENTRIES_82576 24
#define E1000_RAR_ENTRIES_82580 24
#define E1000_SW_SYNCH_MB 0x00000100
#define E1000_STAT_DEV_RST_SET 0x00100000
#define E1000_CTRL_DEV_RST 0x20000000
/* SRRCTL bit definitions */ /* SRRCTL bit definitions */
#define E1000_SRRCTL_BSIZEPKT_SHIFT 10 /* Shift _right_ */ #define E1000_SRRCTL_BSIZEPKT_SHIFT 10 /* Shift _right_ */
...@@ -232,5 +237,6 @@ struct e1000_adv_tx_context_desc { ...@@ -232,5 +237,6 @@ struct e1000_adv_tx_context_desc {
#define E1000_RXPBS_SIZE_MASK_82576 0x0000007F #define E1000_RXPBS_SIZE_MASK_82576 0x0000007F
void igb_vmdq_set_loopback_pf(struct e1000_hw *, bool); void igb_vmdq_set_loopback_pf(struct e1000_hw *, bool);
void igb_vmdq_set_replication_pf(struct e1000_hw *, bool); void igb_vmdq_set_replication_pf(struct e1000_hw *, bool);
u16 igb_rxpbs_adjust_82580(u32 data);
#endif #endif
...@@ -49,6 +49,7 @@ ...@@ -49,6 +49,7 @@
#define E1000_CTRL_EXT_PFRSTD 0x00004000 #define E1000_CTRL_EXT_PFRSTD 0x00004000
#define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000 #define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
#define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000 #define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000
#define E1000_CTRL_EXT_LINK_MODE_1000BASE_KX 0x00400000
#define E1000_CTRL_EXT_LINK_MODE_SGMII 0x00800000 #define E1000_CTRL_EXT_LINK_MODE_SGMII 0x00800000
#define E1000_CTRL_EXT_EIAME 0x01000000 #define E1000_CTRL_EXT_EIAME 0x01000000
#define E1000_CTRL_EXT_IRCA 0x00000001 #define E1000_CTRL_EXT_IRCA 0x00000001
...@@ -557,8 +558,12 @@ ...@@ -557,8 +558,12 @@
#define NVM_ALT_MAC_ADDR_PTR 0x0037 #define NVM_ALT_MAC_ADDR_PTR 0x0037
#define NVM_CHECKSUM_REG 0x003F #define NVM_CHECKSUM_REG 0x003F
#define E1000_NVM_CFG_DONE_PORT_0 0x40000 /* MNG config cycle done */ #define E1000_NVM_CFG_DONE_PORT_0 0x040000 /* MNG config cycle done */
#define E1000_NVM_CFG_DONE_PORT_1 0x80000 /* ...for second port */ #define E1000_NVM_CFG_DONE_PORT_1 0x080000 /* ...for second port */
#define E1000_NVM_CFG_DONE_PORT_2 0x100000 /* ...for third port */
#define E1000_NVM_CFG_DONE_PORT_3 0x200000 /* ...for fourth port */
#define NVM_82580_LAN_FUNC_OFFSET(a) (a ? (0x40 + (0x40 * a)) : 0)
/* Mask bits for fields in Word 0x0f of the NVM */ /* Mask bits for fields in Word 0x0f of the NVM */
#define NVM_WORD0F_PAUSE_MASK 0x3000 #define NVM_WORD0F_PAUSE_MASK 0x3000
...@@ -625,6 +630,7 @@ ...@@ -625,6 +630,7 @@
*/ */
#define M88E1111_I_PHY_ID 0x01410CC0 #define M88E1111_I_PHY_ID 0x01410CC0
#define IGP03E1000_E_PHY_ID 0x02A80390 #define IGP03E1000_E_PHY_ID 0x02A80390
#define I82580_I_PHY_ID 0x015403A0
#define M88_VENDOR 0x0141 #define M88_VENDOR 0x0141
/* M88E1000 Specific Registers */ /* M88E1000 Specific Registers */
......
...@@ -47,19 +47,30 @@ struct e1000_hw; ...@@ -47,19 +47,30 @@ struct e1000_hw;
#define E1000_DEV_ID_82575EB_COPPER 0x10A7 #define E1000_DEV_ID_82575EB_COPPER 0x10A7
#define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9 #define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9
#define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6 #define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6
#define E1000_DEV_ID_82580_COPPER 0x150E
#define E1000_DEV_ID_82580_FIBER 0x150F
#define E1000_DEV_ID_82580_SERDES 0x1510
#define E1000_DEV_ID_82580_SGMII 0x1511
#define E1000_DEV_ID_82580_COPPER_DUAL 0x1516
#define E1000_REVISION_2 2 #define E1000_REVISION_2 2
#define E1000_REVISION_4 4 #define E1000_REVISION_4 4
#define E1000_FUNC_0 0 #define E1000_FUNC_0 0
#define E1000_FUNC_1 1 #define E1000_FUNC_1 1
#define E1000_FUNC_2 2
#define E1000_FUNC_3 3
#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0
#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3
#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2 6
#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3 9
enum e1000_mac_type { enum e1000_mac_type {
e1000_undefined = 0, e1000_undefined = 0,
e1000_82575, e1000_82575,
e1000_82576, e1000_82576,
e1000_82580,
e1000_num_macs /* List is 1-based, so subtract 1 for true count. */ e1000_num_macs /* List is 1-based, so subtract 1 for true count. */
}; };
...@@ -290,6 +301,7 @@ struct e1000_mac_operations { ...@@ -290,6 +301,7 @@ struct e1000_mac_operations {
struct e1000_phy_operations { struct e1000_phy_operations {
s32 (*acquire)(struct e1000_hw *); s32 (*acquire)(struct e1000_hw *);
s32 (*check_polarity)(struct e1000_hw *);
s32 (*check_reset_block)(struct e1000_hw *); s32 (*check_reset_block)(struct e1000_hw *);
s32 (*force_speed_duplex)(struct e1000_hw *); s32 (*force_speed_duplex)(struct e1000_hw *);
s32 (*get_cfg_done)(struct e1000_hw *hw); s32 (*get_cfg_done)(struct e1000_hw *hw);
...@@ -466,6 +478,7 @@ struct e1000_mbx_info { ...@@ -466,6 +478,7 @@ struct e1000_mbx_info {
struct e1000_dev_spec_82575 { struct e1000_dev_spec_82575 {
bool sgmii_active; bool sgmii_active;
bool global_device_reset;
}; };
struct e1000_hw { struct e1000_hw {
......
...@@ -136,7 +136,7 @@ static s32 igb_phy_reset_dsp(struct e1000_hw *hw) ...@@ -136,7 +136,7 @@ static s32 igb_phy_reset_dsp(struct e1000_hw *hw)
* Reads the MDI control regsiter in the PHY at offset and stores the * Reads the MDI control regsiter in the PHY at offset and stores the
* information read to data. * information read to data.
**/ **/
static s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data) s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
{ {
struct e1000_phy_info *phy = &hw->phy; struct e1000_phy_info *phy = &hw->phy;
u32 i, mdic = 0; u32 i, mdic = 0;
...@@ -194,7 +194,7 @@ static s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data) ...@@ -194,7 +194,7 @@ static s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
* *
* Writes data to MDI control register in the PHY at offset. * Writes data to MDI control register in the PHY at offset.
**/ **/
static s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data) s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
{ {
struct e1000_phy_info *phy = &hw->phy; struct e1000_phy_info *phy = &hw->phy;
u32 i, mdic = 0; u32 i, mdic = 0;
...@@ -1947,7 +1947,7 @@ s32 igb_phy_init_script_igp3(struct e1000_hw *hw) ...@@ -1947,7 +1947,7 @@ s32 igb_phy_init_script_igp3(struct e1000_hw *hw)
* *
* Polarity is determined based on the PHY specific status register. * Polarity is determined based on the PHY specific status register.
**/ **/
s32 igb_check_polarity_82580(struct e1000_hw *hw) static s32 igb_check_polarity_82580(struct e1000_hw *hw)
{ {
struct e1000_phy_info *phy = &hw->phy; struct e1000_phy_info *phy = &hw->phy;
s32 ret_val; s32 ret_val;
......
...@@ -61,10 +61,11 @@ s32 igb_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data); ...@@ -61,10 +61,11 @@ s32 igb_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data);
s32 igb_phy_has_link(struct e1000_hw *hw, u32 iterations, s32 igb_phy_has_link(struct e1000_hw *hw, u32 iterations,
u32 usec_interval, bool *success); u32 usec_interval, bool *success);
s32 igb_phy_init_script_igp3(struct e1000_hw *hw); s32 igb_phy_init_script_igp3(struct e1000_hw *hw);
s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data);
s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data);
s32 igb_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data); s32 igb_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data);
s32 igb_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data); s32 igb_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data);
s32 igb_copper_link_setup_82580(struct e1000_hw *hw); s32 igb_copper_link_setup_82580(struct e1000_hw *hw);
s32 igb_check_polarity_82580(struct e1000_hw *hw);
s32 igb_get_phy_info_82580(struct e1000_hw *hw); s32 igb_get_phy_info_82580(struct e1000_hw *hw);
s32 igb_phy_force_speed_duplex_82580(struct e1000_hw *hw); s32 igb_phy_force_speed_duplex_82580(struct e1000_hw *hw);
s32 igb_get_cable_length_82580(struct e1000_hw *hw); s32 igb_get_cable_length_82580(struct e1000_hw *hw);
......
...@@ -34,6 +34,7 @@ ...@@ -34,6 +34,7 @@
#define E1000_EERD 0x00014 /* EEPROM Read - RW */ #define E1000_EERD 0x00014 /* EEPROM Read - RW */
#define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */ #define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */
#define E1000_MDIC 0x00020 /* MDI Control - RW */ #define E1000_MDIC 0x00020 /* MDI Control - RW */
#define E1000_MDICNFG 0x00E04 /* MDI Config - RW */
#define E1000_SCTL 0x00024 /* SerDes Control - RW */ #define E1000_SCTL 0x00024 /* SerDes Control - RW */
#define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */ #define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */
#define E1000_FCAH 0x0002C /* Flow Control Address High -RW */ #define E1000_FCAH 0x0002C /* Flow Control Address High -RW */
......
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