Commit bb2dc7f4 authored by Tudor Ambarus's avatar Tudor Ambarus

mtd: spi-nor: Rename CR_QUAD_EN_SPAN to SR2_QUAD_EN_BIT1

JEDEC Basic Flash Parameter Table, 15th DWORD, bits 22:20,
refers to this bit as "bit 1 of the status register 2".
Rename the macro accordingly.
Signed-off-by: default avatarTudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: default avatarVignesh Raghavendra <vigneshr@ti.com>
parent 4da11da1
......@@ -1026,7 +1026,7 @@ static int spi_nor_write_16bit_sr_and_check(struct spi_nor *nor, u8 sr1)
* Write Status (01h) command is available just for the cases
* in which the QE bit is described in SR2 at BIT(1).
*/
sr_cr[1] = CR_QUAD_EN_SPAN;
sr_cr[1] = SR2_QUAD_EN_BIT1;
} else {
sr_cr[1] = 0;
}
......@@ -2074,7 +2074,7 @@ static int spansion_no_read_cr_quad_enable(struct spi_nor *nor)
if (ret)
return ret;
sr_cr[1] = CR_QUAD_EN_SPAN;
sr_cr[1] = SR2_QUAD_EN_BIT1;
ret = spi_nor_write_sr(nor, sr_cr, 2);
if (ret)
......@@ -2118,10 +2118,10 @@ static int spansion_read_cr_quad_enable(struct spi_nor *nor)
if (ret)
return ret;
if (sr_cr[1] & CR_QUAD_EN_SPAN)
if (sr_cr[1] & SR2_QUAD_EN_BIT1)
return 0;
sr_cr[1] |= CR_QUAD_EN_SPAN;
sr_cr[1] |= SR2_QUAD_EN_BIT1;
/* Keep the current value of the Status Register. */
ret = spi_nor_read_sr(nor, sr_cr);
......
......@@ -144,10 +144,8 @@
#define FSR_P_ERR BIT(4) /* Program operation status */
#define FSR_PT_ERR BIT(1) /* Protection error bit */
/* Configuration Register bits. */
#define CR_QUAD_EN_SPAN BIT(1) /* Spansion Quad I/O */
/* Status Register 2 bits. */
#define SR2_QUAD_EN_BIT1 BIT(1)
#define SR2_QUAD_EN_BIT7 BIT(7)
/* Supported SPI protocols */
......
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